__u32 insn;
long si_code;
- MOD_INC_USE_COUNT;
-
- get_user(insn, (__u32*)pc);
+ get_user(insn, (__u32 __user *)pc);
fc = (insn >> 0) & 0x1f; /* destination register */
fb = (insn >> 16) & 0x1f;
fa = (insn >> 21) & 0x1f;
_FP_FRAC_SET_1(DB, _FP_ZEROFRAC_1);
}
FP_CMP_D(res, DA, DB, 3);
- vc = 0x4000000000000000;
+ vc = 0x4000000000000000UL;
/* CMPTEQ, CMPTUN don't trap on QNaN,
while CMPTLT and CMPTLE do */
if (res == 3
if (_fex & IEEE_TRAP_ENABLE_INV) si_code = FPE_FLTINV;
}
- MOD_DEC_USE_COUNT;
return si_code;
}
requires that the result *always* be written... so we do the write
immediately after the operations above. */
- MOD_DEC_USE_COUNT;
return 0;
bad_insn:
printk(KERN_ERR "alpha_fp_emul: Invalid FP insn %#x at %#lx\n",
insn, pc);
- MOD_DEC_USE_COUNT;
return -1;
}
unsigned long trigger_pc = regs->pc - 4;
unsigned long insn, opcode, rc, si_code = 0;
- MOD_INC_USE_COUNT;
-
/*
* Turn off the bits corresponding to registers that are the
* target of instructions that set bits in the exception
* up to the first occurrence of such an instruction.
*/
while (write_mask) {
- get_user(insn, (__u32*)(trigger_pc));
+ get_user(insn, (__u32 __user *)(trigger_pc));
opcode = insn >> 26;
rc = insn & 0x1f;
}
egress:
- MOD_DEC_USE_COUNT;
return si_code;
}