vserver 1.9.3

[linux-2.6.git] / arch / arm / boot / compressed / head.S

diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S
index b47032c..f560cbf 100644 (file)
--- a/arch/arm/boot/compressed/head.S
+++ b/arch/arm/boot/compressed/head.S
@@ -79,6 +79,14 @@
                .endm
                .macro  writeb, rb
                str     \rb, [r3, #0]
+#elif defined(CONFIG_ARCH_IXP2000)
+               .macro  loadsp, rb
+               mov     \rb, #0xc0000000
+               orr     \rb, \rb, #0x00030000
+               .endm
+               .macro  writeb, rb
+               str     \rb, [r3, #0]
+               .endm
 #elif defined(CONFIG_ARCH_LH7A40X)
                .macro  loadsp, rb
                ldr     \rb, =0x80000700        @ UART2 UARTBASE
@@ -100,6 +108,15 @@
                .macro  writeb, rb
                strb    \rb, [r3]
                .endm
+#elif defined(CONFIG_ARCH_IOP331)
+               .macro loadsp, rb
+                mov    \rb, #0xff000000
+                orr     \rb, \rb, #0x00ff0000
+                orr     \rb, \rb, #0x0000f700   @ location of the UART
+               .endm
+               .macro  writeb, rb
+               str     \rb, [r3, #0]
+               .endm
 #else
 #error no serial architecture defined
 #endif
@@ -332,6 +349,14 @@ LC0:               .word   LC0                     @ r1
 LC1:           .word   reloc_end - reloc_start
                .size   LC0, . - LC0
 
+#ifdef CONFIG_ARCH_RPC
+               .globl  params
+params:                ldr     r0, =params_phys
+               mov     pc, lr
+               .ltorg
+               .align
+#endif
+
 /*
  * Turn on the cache.  We need to setup some page tables so that we
  * can have both the I and D caches on.
@@ -568,6 +593,12 @@ proc_types:
                b       __armv4_cache_off
                b       __armv4_cache_flush
 
+               .word   0x00070000              @ ARMv6
+               .word   0x000f0000
+               b       __armv4_cache_on
+               b       __armv4_cache_off
+               b       __armv6_cache_flush
+
                .word   0                       @ unrecognised type
                .word   0
                mov     pc, lr
@@ -627,6 +658,14 @@ cache_clean_flush:
                mov     r3, #16
                b       call_cache_fn
 
+__armv6_cache_flush:
+               mov     r1, #0
+               mcr     p15, 0, r1, c7, c14, 0  @ clean+invalidate D
+               mcr     p15, 0, r1, c7, c5, 0   @ invalidate I+BTB
+               mcr     p15, 0, r1, c7, c15, 0  @ clean+invalidate unified
+               mcr     p15, 0, r1, c7, c10, 4  @ drain WB
+               mov     pc, lr
+
 __armv4_cache_flush:
                mov     r2, #64*1024            @ default: 32K dcache size (*2)
                mov     r11, #32                @ default: 32 byte line size