#include <asm/irq.h>
#include <asm/arch/irqs.h>
#include <asm/arch/gpio.h>
-#include <asm/arch/pm.h>
#include <asm/mach/irq.h>
#include <asm/io.h>
#define OMAP730_GPIO_INT_MASK 0x10
#define OMAP730_GPIO_INT_STATUS 0x14
-#define OMAP_MPUIO_MASK (~OMAP_MAX_GPIO_LINES & 0xff)
+#define OMAP_MPUIO_MASK (~OMAP_MAX_GPIO_LINES & 0xff)
struct gpio_bank {
u32 base;
reg += OMAP730_GPIO_DIR_CONTROL;
break;
}
- l = omap_readl(reg);
+ l = __raw_readl(reg);
if (is_input)
l |= 1 << gpio;
else
l &= ~(1 << gpio);
- omap_writel(l, reg);
+ __raw_writel(l, reg);
}
void omap_set_gpio_direction(int gpio, int is_input)
switch (bank->method) {
case METHOD_MPUIO:
- reg += OMAP_MPUIO_OUTPUT_REG;
- l = omap_readl(reg);
+ reg += OMAP_MPUIO_OUTPUT;
+ l = __raw_readl(reg);
if (enable)
l |= 1 << gpio;
else
break;
case METHOD_GPIO_1510:
reg += OMAP1510_GPIO_DATA_OUTPUT;
- l = omap_readl(reg);
+ l = __raw_readl(reg);
if (enable)
l |= 1 << gpio;
else
break;
case METHOD_GPIO_730:
reg += OMAP730_GPIO_DATA_OUTPUT;
- l = omap_readl(reg);
+ l = __raw_readl(reg);
if (enable)
l |= 1 << gpio;
else
BUG();
return;
}
- omap_writel(l, reg);
+ __raw_writel(l, reg);
}
void omap_set_gpio_dataout(int gpio, int enable)
BUG();
return -1;
}
- return (omap_readl(reg) & (1 << get_gpio_index(gpio))) != 0;
+ return (__raw_readl(reg) & (1 << get_gpio_index(gpio))) != 0;
}
static void _set_gpio_edge_ctrl(struct gpio_bank *bank, int gpio, int edge)
switch (bank->method) {
case METHOD_MPUIO:
- reg += OMAP_MPUIO_GPIO_INT_EDGE_REG;
- l = omap_readl(reg);
+ reg += OMAP_MPUIO_GPIO_INT_EDGE;
+ l = __raw_readl(reg);
if (edge == OMAP_GPIO_RISING_EDGE)
l |= 1 << gpio;
else
l &= ~(1 << gpio);
- omap_writel(l, reg);
+ __raw_writel(l, reg);
break;
case METHOD_GPIO_1510:
reg += OMAP1510_GPIO_INT_CONTROL;
- l = omap_readl(reg);
+ l = __raw_readl(reg);
if (edge == OMAP_GPIO_RISING_EDGE)
l |= 1 << gpio;
else
l &= ~(1 << gpio);
- omap_writel(l, reg);
+ __raw_writel(l, reg);
break;
case METHOD_GPIO_1610:
edge &= 0x03;
else
reg += OMAP1610_GPIO_EDGE_CTRL1;
gpio &= 0x07;
- l = omap_readl(reg);
+ l = __raw_readl(reg);
l &= ~(3 << (gpio << 1));
l |= edge << (gpio << 1);
- omap_writel(l, reg);
+ __raw_writel(l, reg);
break;
case METHOD_GPIO_730:
reg += OMAP730_GPIO_INT_CONTROL;
- l = omap_readl(reg);
+ l = __raw_readl(reg);
if (edge == OMAP_GPIO_RISING_EDGE)
l |= 1 << gpio;
else
l &= ~(1 << gpio);
- omap_writel(l, reg);
+ __raw_writel(l, reg);
break;
default:
BUG();
switch (bank->method) {
case METHOD_MPUIO:
- l = omap_readl(reg + OMAP_MPUIO_GPIO_INT_EDGE_REG);
+ l = __raw_readl(reg + OMAP_MPUIO_GPIO_INT_EDGE);
return (l & (1 << gpio)) ?
OMAP_GPIO_RISING_EDGE : OMAP_GPIO_FALLING_EDGE;
case METHOD_GPIO_1510:
- l = omap_readl(reg + OMAP1510_GPIO_INT_CONTROL);
+ l = __raw_readl(reg + OMAP1510_GPIO_INT_CONTROL);
return (l & (1 << gpio)) ?
OMAP_GPIO_RISING_EDGE : OMAP_GPIO_FALLING_EDGE;
case METHOD_GPIO_1610:
reg += OMAP1610_GPIO_EDGE_CTRL2;
else
reg += OMAP1610_GPIO_EDGE_CTRL1;
- return (omap_readl(reg) >> ((gpio & 0x07) << 1)) & 0x03;
+ return (__raw_readl(reg) >> ((gpio & 0x07) << 1)) & 0x03;
case METHOD_GPIO_730:
- l = omap_readl(reg + OMAP730_GPIO_INT_CONTROL);
+ l = __raw_readl(reg + OMAP730_GPIO_INT_CONTROL);
return (l & (1 << gpio)) ?
OMAP_GPIO_RISING_EDGE : OMAP_GPIO_FALLING_EDGE;
default:
BUG();
return;
}
- omap_writel(1 << get_gpio_index(gpio), reg);
+ __raw_writel(1 << get_gpio_index(gpio), reg);
}
static void _set_gpio_irqenable(struct gpio_bank *bank, int gpio, int enable)
switch (bank->method) {
case METHOD_MPUIO:
reg += OMAP_MPUIO_GPIO_MASKIT;
- l = omap_readl(reg);
+ l = __raw_readl(reg);
if (enable)
l &= ~(1 << gpio);
else
break;
case METHOD_GPIO_1510:
reg += OMAP1510_GPIO_INT_MASK;
- l = omap_readl(reg);
+ l = __raw_readl(reg);
if (enable)
l &= ~(1 << gpio);
else
break;
case METHOD_GPIO_730:
reg += OMAP730_GPIO_INT_MASK;
- l = omap_readl(reg);
+ l = __raw_readl(reg);
if (enable)
l &= ~(1 << gpio);
else
BUG();
return;
}
- omap_writel(l, reg);
+ __raw_writel(l, reg);
}
int omap_request_gpio(int gpio)
/* Claim the pin for the ARM */
reg = bank->base + OMAP1510_GPIO_PIN_CONTROL;
- omap_writel(omap_readl(reg) | (1 << get_gpio_index(gpio)), reg);
+ __raw_writel(__raw_readl(reg) | (1 << get_gpio_index(gpio)), reg);
}
#endif
spin_unlock(&bank->lock);
isr_reg = bank->base + OMAP730_GPIO_INT_STATUS;
#endif
for (;;) {
- u32 isr = omap_readl(isr_reg);
+ u32 isr = __raw_readl(isr_reg);
unsigned int gpio_irq;
if (!isr)
#ifdef CONFIG_ARCH_OMAP1510
if (bank->method == METHOD_GPIO_1510)
- omap_writew(1 << gpio, bank->base + OMAP1510_GPIO_INT_STATUS);
+ __raw_writew(1 << (gpio & 0x0f), bank->base + OMAP1510_GPIO_INT_STATUS);
#endif
#if defined(CONFIG_ARCH_OMAP1610) || defined(CONFIG_ARCH_OMAP5912)
if (bank->method == METHOD_GPIO_1610)
- omap_writew(1 << gpio, bank->base + OMAP1610_GPIO_IRQSTATUS1);
+ __raw_writew(1 << (gpio & 0x0f), bank->base + OMAP1610_GPIO_IRQSTATUS1);
#endif
#ifdef CONFIG_ARCH_OMAP730
if (bank->method == METHOD_GPIO_730)
- omap_writel(1 << gpio, bank->base + OMAP730_GPIO_INT_STATUS);
+ __raw_writel(1 << (gpio & 0x1f), bank->base + OMAP730_GPIO_INT_STATUS);
#endif
}
bank = &gpio_bank[i];
bank->reserved_map = 0;
+ bank->base = IO_ADDRESS(bank->base);
spin_lock_init(&bank->lock);
if (bank->method == METHOD_MPUIO) {
omap_writew(0xFFFF, OMAP_MPUIO_BASE + OMAP_MPUIO_GPIO_MASKIT);
}
#ifdef CONFIG_ARCH_OMAP1510
if (bank->method == METHOD_GPIO_1510) {
- omap_writew(0xffff, bank->base + OMAP1510_GPIO_INT_MASK);
- omap_writew(0x0000, bank->base + OMAP1510_GPIO_INT_STATUS);
+ __raw_writew(0xffff, bank->base + OMAP1510_GPIO_INT_MASK);
+ __raw_writew(0x0000, bank->base + OMAP1510_GPIO_INT_STATUS);
}
#endif
#if defined(CONFIG_ARCH_OMAP1610) || defined(CONFIG_ARCH_OMAP5912)
if (bank->method == METHOD_GPIO_1610) {
- omap_writew(0x0000, bank->base + OMAP1610_GPIO_IRQENABLE1);
- omap_writew(0xffff, bank->base + OMAP1610_GPIO_IRQSTATUS1);
+ __raw_writew(0x0000, bank->base + OMAP1610_GPIO_IRQENABLE1);
+ __raw_writew(0xffff, bank->base + OMAP1610_GPIO_IRQSTATUS1);
}
#endif
#ifdef CONFIG_ARCH_OMAP730
if (bank->method == METHOD_GPIO_730) {
- omap_writel(0xffffffff, bank->base + OMAP730_GPIO_INT_MASK);
- omap_writel(0x00000000, bank->base + OMAP730_GPIO_INT_STATUS);
+ __raw_writel(0xffffffff, bank->base + OMAP730_GPIO_INT_MASK);
+ __raw_writel(0x00000000, bank->base + OMAP730_GPIO_INT_STATUS);
gpio_count = 32; /* 730 has 32-bit GPIOs */
}
}
/* Enable system clock for GPIO module.
- * The CAM_CLK_CTRL_REG *is* really the right place. */
+ * The CAM_CLK_CTRL *is* really the right place. */
if (cpu_is_omap1610())
- omap_writel(omap_readl(ULPD_CAM_CLK_CTRL_REG) | 0x04, ULPD_CAM_CLK_CTRL_REG);
+ omap_writel(omap_readl(ULPD_CAM_CLK_CTRL) | 0x04, ULPD_CAM_CLK_CTRL);
return 0;
}
return 0;
}
-EXPORT_SYMBOL(omap_gpio_init);
EXPORT_SYMBOL(omap_request_gpio);
EXPORT_SYMBOL(omap_free_gpio);
+EXPORT_SYMBOL(omap_set_gpio_direction);
+EXPORT_SYMBOL(omap_set_gpio_dataout);
+EXPORT_SYMBOL(omap_get_gpio_datain);
+EXPORT_SYMBOL(omap_set_gpio_edge_ctrl);
arch_initcall(omap_gpio_init);