vserver 2.0 rc7

[linux-2.6.git] / arch / arm / mm / Kconfig

diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig
index 5b670c9..3fefb43 100644 (file)
--- a/arch/arm/mm/Kconfig
+++ b/arch/arm/mm/Kconfig
@@ -228,7 +228,6 @@ config CPU_SA1100
        select CPU_CACHE_V4WB
        select CPU_CACHE_VIVT
        select CPU_TLB_V4WB
-       select CPU_MINICACHE
 
 # XScale
 config CPU_XSCALE
@@ -239,7 +238,6 @@ config CPU_XSCALE
        select CPU_ABRT_EV5T
        select CPU_CACHE_VIVT
        select CPU_TLB_V4WBI
-       select CPU_MINICACHE
 
 # ARMv6
 config CPU_V6
@@ -345,11 +343,6 @@ config CPU_TLB_V4WBI
 config CPU_TLB_V6
        bool
 
-config CPU_MINICACHE
-       bool
-       help
-         Processor has a minicache.
-
 comment "Processor Features"
 
 config ARM_THUMB
@@ -409,3 +402,31 @@ config CPU_BPREDICT_DISABLE
        depends on CPU_ARM1020
        help
          Say Y here to disable branch prediction.  If unsure, say N.
+
+config TLS_REG_EMUL
+       bool
+       default y if SMP && (CPU_32v5 || CPU_32v4 || CPU_32v3)
+       help
+         An SMP system using a pre-ARMv6 processor (there are apparently
+         a few prototypes like that in existence) and therefore access to
+         that required register must be emulated.
+
+config HAS_TLS_REG
+       bool
+       depends on !TLS_REG_EMUL
+       default y if SMP || CPU_32v7
+       help
+         This selects support for the CP15 thread register.
+         It is defined to be available on some ARMv6 processors (including
+         all SMP capable ARMv6's) or later processors.  User space may
+         assume directly accessing that register and always obtain the
+         expected value only on ARMv7 and above.
+
+config NEEDS_SYSCALL_FOR_CMPXCHG
+       bool
+       default y if SMP && (CPU_32v5 || CPU_32v4 || CPU_32v3)
+       help
+         SMP on a pre-ARMv6 processor?  Well OK then.
+         Forget about fast user space cmpxchg support.
+         It is just not possible.
+