depends on ARCH_RPC
select CPU_32v3
select CPU_CACHE_V3
- select CPU_COPY_V3
- select CPU_TLB_V3
+ select CPU_CACHE_VIVT
+ select CPU_COPY_V3 if MMU
+ select CPU_TLB_V3 if MMU
help
The ARM610 is the successor to the ARM3 processor
and was produced by VLSI Technology Inc.
default y if ARCH_CLPS7500
select CPU_32v3
select CPU_CACHE_V3
- select CPU_COPY_V3
- select CPU_TLB_V3
+ select CPU_CACHE_VIVT
+ select CPU_COPY_V3 if MMU
+ select CPU_TLB_V3 if MMU
help
A 32-bit RISC microprocessor based on the ARM7 processor core
designed by Advanced RISC Machines Ltd. The ARM710 is the
# ARM720T
config CPU_ARM720T
bool "Support ARM720T processor" if !ARCH_CLPS711X && !ARCH_L7200 && !ARCH_CDB89712 && ARCH_INTEGRATOR
- default y if ARCH_CLPS711X || ARCH_L7200 || ARCH_CDB89712
- select CPU_32v4
+ default y if ARCH_CLPS711X || ARCH_L7200 || ARCH_CDB89712 || ARCH_H720X
+ select CPU_32v4T
select CPU_ABRT_LV4T
select CPU_CACHE_V4
- select CPU_COPY_V4WT
- select CPU_TLB_V4WT
+ select CPU_CACHE_VIVT
+ select CPU_COPY_V4WT if MMU
+ select CPU_TLB_V4WT if MMU
help
A 32-bit RISC processor with 8kByte Cache, Write Buffer and
MMU built around an ARM7TDMI core.
# ARM920T
config CPU_ARM920T
- bool "Support ARM920T processor" if !ARCH_S3C2410
- depends on ARCH_INTEGRATOR || ARCH_S3C2410
- default y if ARCH_S3C2410
- select CPU_32v4
+ bool "Support ARM920T processor"
+ depends on ARCH_EP93XX || ARCH_INTEGRATOR || CPU_S3C2410 || CPU_S3C2440 || CPU_S3C2442 || ARCH_IMX || ARCH_AAEC2000 || ARCH_AT91RM9200
+ default y if CPU_S3C2410 || CPU_S3C2440 || CPU_S3C2442 || ARCH_AT91RM9200
+ select CPU_32v4T
select CPU_ABRT_EV4T
select CPU_CACHE_V4WT
- select CPU_COPY_V4WB
- select CPU_TLB_V4WBI
+ select CPU_CACHE_VIVT
+ select CPU_COPY_V4WB if MMU
+ select CPU_TLB_V4WBI if MMU
help
The ARM920T is licensed to be produced by numerous vendors,
and is used in the Maverick EP9312 and the Samsung S3C2410.
# ARM922T
config CPU_ARM922T
- bool
- depends on ARCH_CAMELOT || ARCH_LH7A40X
- default y
- select CPU_32v4
+ bool "Support ARM922T processor" if ARCH_INTEGRATOR
+ depends on ARCH_LH7A40X || ARCH_INTEGRATOR
+ default y if ARCH_LH7A40X
+ select CPU_32v4T
select CPU_ABRT_EV4T
select CPU_CACHE_V4WT
- select CPU_COPY_V4WB
- select CPU_TLB_V4WBI
+ select CPU_CACHE_VIVT
+ select CPU_COPY_V4WB if MMU
+ select CPU_TLB_V4WBI if MMU
help
The ARM922T is a version of the ARM920T, but with smaller
instruction and data caches. It is used in Altera's
# ARM925T
config CPU_ARM925T
- bool
- depends on ARCH_OMAP1510
- default y
- select CPU_32v4
+ bool "Support ARM925T processor" if ARCH_OMAP1
+ depends on ARCH_OMAP15XX
+ default y if ARCH_OMAP15XX
+ select CPU_32v4T
select CPU_ABRT_EV4T
select CPU_CACHE_V4WT
- select CPU_COPY_V4WB
- select CPU_TLB_V4WBI
+ select CPU_CACHE_VIVT
+ select CPU_COPY_V4WB if MMU
+ select CPU_TLB_V4WBI if MMU
help
The ARM925T is a mix between the ARM920T and ARM926T, but with
different instruction and data caches. It is used in TI's OMAP
# ARM926T
config CPU_ARM926T
- bool "Support ARM926T processor" if ARCH_INTEGRATOR
- depends on ARCH_INTEGRATOR || ARCH_VERSATILE_PB || ARCH_OMAP730 || ARCH_OMAP1610 || ARCH_OMAP5912
- default y if ARCH_VERSATILE_PB
+ bool "Support ARM926T processor"
+ depends on ARCH_INTEGRATOR || ARCH_VERSATILE_PB || MACH_VERSATILE_AB || ARCH_OMAP730 || ARCH_OMAP16XX || MACH_REALVIEW_EB || ARCH_PNX4008 || ARCH_NETX || CPU_S3C2412 || ARCH_AT91SAM9260 || ARCH_AT91SAM9261
+ default y if ARCH_VERSATILE_PB || MACH_VERSATILE_AB || ARCH_OMAP730 || ARCH_OMAP16XX || ARCH_PNX4008 || ARCH_NETX || CPU_S3C2412 || ARCH_AT91SAM9260 || ARCH_AT91SAM9261
select CPU_32v5
select CPU_ABRT_EV5TJ
- select CPU_COPY_V4WB
- select CPU_TLB_V4WBI
+ select CPU_CACHE_VIVT
+ select CPU_COPY_V4WB if MMU
+ select CPU_TLB_V4WBI if MMU
help
This is a variant of the ARM920. It has slightly different
instruction sequences for cache and TLB operations. Curiously,
select CPU_32v5
select CPU_ABRT_EV4T
select CPU_CACHE_V4WT
- select CPU_COPY_V4WB
- select CPU_TLB_V4WBI
+ select CPU_CACHE_VIVT
+ select CPU_COPY_V4WB if MMU
+ select CPU_TLB_V4WBI if MMU
help
The ARM1020 is the 32K cached version of the ARM10 processor,
with an addition of a floating-point unit.
select CPU_32v5
select CPU_ABRT_EV4T
select CPU_CACHE_V4WT
- select CPU_COPY_V4WB
- select CPU_TLB_V4WBI
+ select CPU_CACHE_VIVT
+ select CPU_COPY_V4WB if MMU
+ select CPU_TLB_V4WBI if MMU
depends on n
# ARM1022E
depends on ARCH_INTEGRATOR
select CPU_32v5
select CPU_ABRT_EV4T
- select CPU_COPY_V4WB # can probably do better
- select CPU_TLB_V4WBI
+ select CPU_CACHE_VIVT
+ select CPU_COPY_V4WB if MMU # can probably do better
+ select CPU_TLB_V4WBI if MMU
help
The ARM1022E is an implementation of the ARMv5TE architecture
based upon the ARM10 integer core with a 16KiB L1 Harvard cache,
depends on ARCH_INTEGRATOR
select CPU_32v5
select CPU_ABRT_EV5T # But need Jazelle, but EV5TJ ignores bit 10
- select CPU_COPY_V4WB # can probably do better
- select CPU_TLB_V4WBI
+ select CPU_CACHE_VIVT
+ select CPU_COPY_V4WB if MMU # can probably do better
+ select CPU_TLB_V4WBI if MMU
help
The ARM1026EJ-S is an implementation of the ARMv5TEJ architecture
based upon the ARM10 integer core.
select CPU_32v4 if !ARCH_RPC
select CPU_ABRT_EV4
select CPU_CACHE_V4WB
- select CPU_COPY_V4WB
- select CPU_TLB_V4WB
+ select CPU_CACHE_VIVT
+ select CPU_COPY_V4WB if MMU
+ select CPU_TLB_V4WB if MMU
help
The Intel StrongARM(R) SA-110 is a 32-bit microprocessor and
is available at five speeds ranging from 100 MHz to 233 MHz.
select CPU_32v4
select CPU_ABRT_EV4
select CPU_CACHE_V4WB
- select CPU_TLB_V4WB
- select CPU_MINICACHE
+ select CPU_CACHE_VIVT
+ select CPU_TLB_V4WB if MMU
# XScale
config CPU_XSCALE
bool
- depends on ARCH_IOP3XX || ARCH_PXA || ARCH_IXP4XX
+ depends on ARCH_IOP3XX || ARCH_PXA || ARCH_IXP4XX || ARCH_IXP2000
+ default y
+ select CPU_32v5
+ select CPU_ABRT_EV5T
+ select CPU_CACHE_VIVT
+ select CPU_TLB_V4WBI if MMU
+
+# XScale Core Version 3
+config CPU_XSC3
+ bool
+ depends on ARCH_IXP23XX
default y
select CPU_32v5
select CPU_ABRT_EV5T
- select CPU_TLB_V4WBI
- select CPU_MINICACHE
+ select CPU_CACHE_VIVT
+ select CPU_TLB_V4WBI if MMU
+ select IO_36
# ARMv6
config CPU_V6
bool "Support ARM V6 processor"
- depends on ARCH_INTEGRATOR
+ depends on ARCH_INTEGRATOR || MACH_REALVIEW_EB || ARCH_OMAP2
select CPU_32v6
select CPU_ABRT_EV6
select CPU_CACHE_V6
- select CPU_COPY_V6
- select CPU_TLB_V6
+ select CPU_CACHE_VIPT
+ select CPU_COPY_V6 if MMU
+ select CPU_TLB_V6 if MMU
+
+# ARMv6k
+config CPU_32v6K
+ bool "Support ARM V6K processor extensions" if !SMP
+ depends on CPU_V6
+ default y if SMP
+ help
+ Say Y here if your ARMv6 processor supports the 'K' extension.
+ This enables the kernel to use some instructions not present
+ on previous processors, and as such a kernel build with this
+ enabled will not boot on processors with do not support these
+ instructions.
# Figure out what processor architecture version we should be using.
# This defines the compiler instruction set which depends on the machine type.
config CPU_32v3
bool
+ select TLS_REG_EMUL if SMP || !MMU
+ select NEEDS_SYSCALL_FOR_CMPXCHG if SMP
config CPU_32v4
bool
+ select TLS_REG_EMUL if SMP || !MMU
+ select NEEDS_SYSCALL_FOR_CMPXCHG if SMP
+
+config CPU_32v4T
+ bool
+ select TLS_REG_EMUL if SMP || !MMU
+ select NEEDS_SYSCALL_FOR_CMPXCHG if SMP
config CPU_32v5
bool
+ select TLS_REG_EMUL if SMP || !MMU
+ select NEEDS_SYSCALL_FOR_CMPXCHG if SMP
config CPU_32v6
bool
config CPU_CACHE_V6
bool
+config CPU_CACHE_VIVT
+ bool
+
+config CPU_CACHE_VIPT
+ bool
+
+if MMU
# The copy-page model
config CPU_COPY_V3
bool
config CPU_TLB_V6
bool
-config CPU_MINICACHE
+endif
+
+#
+# CPU supports 36-bit I/O
+#
+config IO_36
bool
- help
- Processor has a minicache.
comment "Processor Features"
config ARM_THUMB
bool "Support Thumb user binaries"
- depends on CPU_ARM720T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM1020 || CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || CPU_XSCALE || CPU_V6
+ depends on CPU_ARM720T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM1020 || CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || CPU_XSCALE || CPU_XSC3 || CPU_V6
default y
help
Say Y if you want to include kernel support for running user space
config CPU_ICACHE_DISABLE
bool "Disable I-Cache"
- depends on CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM1020
+ depends on CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM1020 || CPU_V6
help
Say Y here to disable the processor instruction cache. Unless
you have a reason not to or are unsure, say N.
config CPU_DCACHE_DISABLE
bool "Disable D-Cache"
- depends on CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM1020
+ depends on CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM1020 || CPU_V6
help
Say Y here to disable the processor data cache. Unless
you have a reason not to or are unsure, say N.
config CPU_DCACHE_WRITETHROUGH
bool "Force write through D-cache"
- depends on (CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM1020) && !CPU_DISABLE_DCACHE
+ depends on (CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM1020 || CPU_V6) && !CPU_DCACHE_DISABLE
+ default y if CPU_ARM925T
help
- Say Y here to use the data cache in writethough mode. Unless you
+ Say Y here to use the data cache in writethrough mode. Unless you
specifically require this or are unsure, say N.
config CPU_CACHE_ROUND_ROBIN
config CPU_BPREDICT_DISABLE
bool "Disable branch prediction"
- depends on CPU_ARM1020
+ depends on CPU_ARM1020 || CPU_V6
help
Say Y here to disable branch prediction. If unsure, say N.
+
+config TLS_REG_EMUL
+ bool
+ help
+ An SMP system using a pre-ARMv6 processor (there are apparently
+ a few prototypes like that in existence) and therefore access to
+ that required register must be emulated.
+
+config HAS_TLS_REG
+ bool
+ depends on !TLS_REG_EMUL
+ default y if SMP || CPU_32v7
+ help
+ This selects support for the CP15 thread register.
+ It is defined to be available on some ARMv6 processors (including
+ all SMP capable ARMv6's) or later processors. User space may
+ assume directly accessing that register and always obtain the
+ expected value only on ARMv7 and above.
+
+config NEEDS_SYSCALL_FOR_CMPXCHG
+ bool
+ help
+ SMP on a pre-ARMv6 processor? Well OK then.
+ Forget about fast user space cmpxchg support.
+ It is just not possible.
+
git://git.onelab.eu / linux-2.6.git / blobdiff