vserver 1.9.3

[linux-2.6.git] / arch / arm / mm / cache-v4wb.S

diff --git a/arch/arm/mm/cache-v4wb.S b/arch/arm/mm/cache-v4wb.S
index 4f7c918..5c4055b 100644 (file)
--- a/arch/arm/mm/cache-v4wb.S
+++ b/arch/arm/mm/cache-v4wb.S
@@ -121,6 +121,19 @@ ENTRY(v4wb_flush_kern_dcache_page)
  *     - end    - virtual end address
  */
 ENTRY(v4wb_coherent_kern_range)
+       /* fall through */
+
+/*
+ *     coherent_user_range(start, end)
+ *
+ *     Ensure coherency between the Icache and the Dcache in the
+ *     region described by start.  If you have non-snooping
+ *     Harvard caches, you need to implement this function.
+ *
+ *     - start  - virtual start address
+ *     - end    - virtual end address
+ */
+ENTRY(v4wb_coherent_user_range)
        bic     r0, r0, #CACHE_DLINESIZE - 1
 1:     mcr     p15, 0, r0, c7, c10, 1          @ clean D entry
        mcr     p15, 0, r0, c7, c6, 1           @ invalidate D entry
@@ -195,6 +208,7 @@ ENTRY(v4wb_cache_fns)
        .long   v4wb_flush_user_cache_all
        .long   v4wb_flush_user_cache_range
        .long   v4wb_coherent_kern_range
+       .long   v4wb_coherent_user_range
        .long   v4wb_flush_kern_dcache_page
        .long   v4wb_dma_inv_range
        .long   v4wb_dma_clean_range