vserver 1.9.3

[linux-2.6.git] / arch / arm / mm / proc-arm1022.S

diff --git a/arch/arm/mm/proc-arm1022.S b/arch/arm/mm/proc-arm1022.S
index 35a5c2f..7c84263 100644 (file)
--- a/arch/arm/mm/proc-arm1022.S
+++ b/arch/arm/mm/proc-arm1022.S
@@ -180,6 +180,19 @@ ENTRY(arm1022_flush_user_cache_range)
  *     - end   - virtual end address
  */
 ENTRY(arm1022_coherent_kern_range)
+       /* FALLTHROUGH */
+
+/*
+ *     coherent_user_range(start, end)
+ *
+ *     Ensure coherency between the Icache and the Dcache in the
+ *     region described by start.  If you have non-snooping
+ *     Harvard caches, you need to implement this function.
+ *
+ *     - start - virtual start address
+ *     - end   - virtual end address
+ */
+ENTRY(arm1022_coherent_user_range)
        mov     ip, #0
        bic     r0, r0, #CACHE_DLINESIZE - 1
 1:
@@ -291,6 +304,7 @@ ENTRY(arm1022_cache_fns)
        .long   arm1022_flush_user_cache_all
        .long   arm1022_flush_user_cache_range
        .long   arm1022_coherent_kern_range
+       .long   arm1022_coherent_user_range
        .long   arm1022_flush_kern_dcache_page
        .long   arm1022_dma_inv_range
        .long   arm1022_dma_clean_range
@@ -475,7 +489,7 @@ __arm1022_proc_info:
        b       __arm1022_setup
        .long   cpu_arch_name
        .long   cpu_elf_name
-       .long   HWCAP_SWP | HWCAP_HALF | HWCAP_THUMB
+       .long   HWCAP_SWP | HWCAP_HALF | HWCAP_THUMB | HWCAP_EDSP
        .long   cpu_arm1022_name
        .long   arm1022_processor_functions
        .long   v4wbi_tlb_fns