linux 2.6.16.38 w/ vs2.0.3-rc1

[linux-2.6.git] / arch / arm / mm / proc-arm1026.S

diff --git a/arch/arm/mm/proc-arm1026.S b/arch/arm/mm/proc-arm1026.S
index d6d84d9..10317e4 100644 (file)
--- a/arch/arm/mm/proc-arm1026.S
+++ b/arch/arm/mm/proc-arm1026.S
@@ -3,7 +3,6 @@
  *
  *  Copyright (C) 2000 ARM Limited
  *  Copyright (C) 2000 Deep Blue Solutions Ltd.
- *  hacked for non-paged-MM by Hyok S. Choi, 2003.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -15,16 +14,14 @@
  * functions on the ARM1026EJ-S.
  */
 #include <linux/linkage.h>
+#include <linux/config.h>
 #include <linux/init.h>
 #include <asm/assembler.h>
 #include <asm/asm-offsets.h>
-#include <asm/pgtable-hwdef.h>
 #include <asm/pgtable.h>
 #include <asm/procinfo.h>
 #include <asm/ptrace.h>
 
-#include "proc-macros.S"
-
 /*
  * This is the maximum size of an area which will be invalidated
  * using the single invalidate entry instructions.  Anything larger
@@ -92,9 +89,7 @@ ENTRY(cpu_arm1026_reset)
        mov     ip, #0
        mcr     p15, 0, ip, c7, c7, 0           @ invalidate I,D caches
        mcr     p15, 0, ip, c7, c10, 4          @ drain WB
-#ifdef CONFIG_MMU
        mcr     p15, 0, ip, c8, c7, 0           @ invalidate I & D TLBs
-#endif
        mrc     p15, 0, ip, c1, c0, 0           @ ctrl register
        bic     ip, ip, #0x000f                 @ ............wcam
        bic     ip, ip, #0x1100                 @ ...i...s........
@@ -331,7 +326,6 @@ ENTRY(cpu_arm1026_dcache_clean_area)
  */
        .align  5
 ENTRY(cpu_arm1026_switch_mm)
-#ifdef CONFIG_MMU
        mov     r1, #0
 #ifndef CONFIG_CPU_DCACHE_DISABLE
 1:     mrc     p15, 0, r15, c7, c14, 3         @ test, clean, invalidate
@@ -343,7 +337,6 @@ ENTRY(cpu_arm1026_switch_mm)
        mcr     p15, 0, r1, c7, c10, 4          @ drain WB
        mcr     p15, 0, r0, c2, c0, 0           @ load page table pointer
        mcr     p15, 0, r1, c8, c7, 0           @ invalidate I & D TLBs
-#endif
        mov     pc, lr
         
 /*
@@ -353,7 +346,6 @@ ENTRY(cpu_arm1026_switch_mm)
  */
        .align  5
 ENTRY(cpu_arm1026_set_pte)
-#ifdef CONFIG_MMU
        str     r1, [r0], #-2048                @ linux version
 
        eor     r1, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY
@@ -381,7 +373,6 @@ ENTRY(cpu_arm1026_set_pte)
 #ifndef CONFIG_CPU_DCACHE_DISABLE
        mcr     p15, 0, r0, c7, c10, 1          @ clean D entry
 #endif
-#endif /* CONFIG_MMU */
        mov     pc, lr
 
 
@@ -392,19 +383,17 @@ __arm1026_setup:
        mov     r0, #0
        mcr     p15, 0, r0, c7, c7              @ invalidate I,D caches on v4
        mcr     p15, 0, r0, c7, c10, 4          @ drain write buffer on v4
-#ifdef CONFIG_MMU
        mcr     p15, 0, r0, c8, c7              @ invalidate I,D TLBs on v4
        mcr     p15, 0, r4, c2, c0              @ load page table pointer
-#endif
 #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
        mov     r0, #4                          @ explicitly disable writeback
        mcr     p15, 7, r0, c15, c0, 0
 #endif
-       adr     r5, arm1026_crval
-       ldmia   r5, {r5, r6}
        mrc     p15, 0, r0, c1, c0              @ get control register v4
+       ldr     r5, arm1026_cr1_clear
        bic     r0, r0, r5
-       orr     r0, r0, r6
+       ldr     r5, arm1026_cr1_set
+       orr     r0, r0, r5
 #ifdef CONFIG_CPU_CACHE_ROUND_ROBIN
        orr     r0, r0, #0x4000                 @ .R.. .... .... ....
 #endif
@@ -417,9 +406,12 @@ __arm1026_setup:
         * .011 1001 ..11 0101
         * 
         */
-       .type   arm1026_crval, #object
-arm1026_crval:
-       crval   clear=0x00007f3f, mmuset=0x00003935, ucset=0x00001934
+       .type   arm1026_cr1_clear, #object
+       .type   arm1026_cr1_set, #object
+arm1026_cr1_clear:
+       .word   0x7f3f
+arm1026_cr1_set:
+       .word   0x3935
 
        __INITDATA
 
@@ -454,7 +446,25 @@ cpu_elf_name:
 
        .type   cpu_arm1026_name, #object
 cpu_arm1026_name:
-       .asciz  "ARM1026EJ-S"
+       .ascii  "ARM1026EJ-S"
+#ifndef CONFIG_CPU_ICACHE_DISABLE
+       .ascii  "i"
+#endif
+#ifndef CONFIG_CPU_DCACHE_DISABLE
+       .ascii  "d"
+#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
+       .ascii  "(wt)"
+#else
+       .ascii  "(wb)"
+#endif
+#endif
+#ifndef CONFIG_CPU_BPREDICT_DISABLE
+       .ascii  "B"
+#endif
+#ifdef CONFIG_CPU_CACHE_ROUND_ROBIN
+       .ascii  "RR"
+#endif
+       .ascii  "\0"
        .size   cpu_arm1026_name, . - cpu_arm1026_name
 
        .align
@@ -465,10 +475,6 @@ cpu_arm1026_name:
 __arm1026_proc_info:
        .long   0x4106a260                      @ ARM 1026EJ-S (v5TEJ)
        .long   0xff0ffff0
-       .long   PMD_TYPE_SECT | \
-               PMD_BIT4 | \
-               PMD_SECT_AP_WRITE | \
-               PMD_SECT_AP_READ
        .long   PMD_TYPE_SECT | \
                PMD_BIT4 | \
                PMD_SECT_AP_WRITE | \