vserver 1.9.3

[linux-2.6.git] / arch / arm / mm / proc-arm926.S

diff --git a/arch/arm/mm/proc-arm926.S b/arch/arm/mm/proc-arm926.S
index 9b098e0..5631c8b 100644 (file)
--- a/arch/arm/mm/proc-arm926.S
+++ b/arch/arm/mm/proc-arm926.S
@@ -185,6 +185,19 @@ ENTRY(arm926_flush_user_cache_range)
  *     - end   - virtual end address
  */
 ENTRY(arm926_coherent_kern_range)
+       /* FALLTHROUGH */
+
+/*
+ *     coherent_user_range(start, end)
+ *
+ *     Ensure coherency between the Icache and the Dcache in the
+ *     region described by start, end.  If you have non-snooping
+ *     Harvard caches, you need to implement this function.
+ *
+ *     - start - virtual start address
+ *     - end   - virtual end address
+ */
+ENTRY(arm926_coherent_user_range)
        bic     r0, r0, #CACHE_DLINESIZE - 1
 1:     mcr     p15, 0, r0, c7, c10, 1          @ clean D entry
        mcr     p15, 0, r0, c7, c5, 1           @ invalidate I entry
@@ -289,6 +302,7 @@ ENTRY(arm926_cache_fns)
        .long   arm926_flush_user_cache_all
        .long   arm926_flush_user_cache_range
        .long   arm926_coherent_kern_range
+       .long   arm926_coherent_user_range
        .long   arm926_flush_kern_dcache_page
        .long   arm926_dma_inv_range
        .long   arm926_dma_clean_range
@@ -473,7 +487,7 @@ __arm926_proc_info:
        b       __arm926_setup
        .long   cpu_arch_name
        .long   cpu_elf_name
-       .long   HWCAP_SWP | HWCAP_HALF | HWCAP_THUMB | HWCAP_FAST_MULT | HWCAP_JAVA
+       .long   HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP|HWCAP_JAVA
        .long   cpu_arm926_name
        .long   arm926_processor_functions
        .long   v4wbi_tlb_fns