linux 2.6.16.38 w/ vs2.0.3-rc1

[linux-2.6.git] / arch / arm / mm / proc-sa110.S

diff --git a/arch/arm/mm/proc-sa110.S b/arch/arm/mm/proc-sa110.S
index c878064..bd330c4 100644 (file)
--- a/arch/arm/mm/proc-sa110.S
+++ b/arch/arm/mm/proc-sa110.S
@@ -2,7 +2,6 @@
  *  linux/arch/arm/mm/proc-sa110.S
  *
  *  Copyright (C) 1997-2002 Russell King
- *  hacked for non-paged-MM by Hyok S. Choi, 2003.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
@@ -19,17 +18,29 @@
 #include <asm/asm-offsets.h>
 #include <asm/procinfo.h>
 #include <asm/hardware.h>
-#include <asm/pgtable-hwdef.h>
 #include <asm/pgtable.h>
 #include <asm/ptrace.h>
 
-#include "proc-macros.S"
-
 /*
  * the cache line size of the I and D cache
  */
 #define DCACHELINESIZE 32
-
+#define FLUSH_OFFSET   32768
+
+       .macro flush_110_dcache rd, ra, re
+       ldr     \rd, =flush_base
+       ldr     \ra, [\rd]
+       eor     \ra, \ra, #FLUSH_OFFSET
+       str     \ra, [\rd]
+       add     \re, \ra, #16384                @ only necessary for 16k
+1001:  ldr     \rd, [\ra], #DCACHELINESIZE
+       teq     \re, \ra
+       bne     1001b
+       .endm
+
+       .data
+flush_base:
+       .long   FLUSH_BASE
        .text
 
 /*
@@ -70,9 +81,7 @@ ENTRY(cpu_sa110_reset)
        mov     ip, #0
        mcr     p15, 0, ip, c7, c7, 0           @ invalidate I,D caches
        mcr     p15, 0, ip, c7, c10, 4          @ drain WB
-#ifdef CONFIG_MMU
        mcr     p15, 0, ip, c8, c7, 0           @ invalidate I & D TLBs
-#endif
        mrc     p15, 0, ip, c1, c0, 0           @ ctrl register
        bic     ip, ip, #0x000f                 @ ............wcam
        bic     ip, ip, #0x1100                 @ ...i...s........
@@ -135,15 +144,13 @@ ENTRY(cpu_sa110_dcache_clean_area)
  */
        .align  5
 ENTRY(cpu_sa110_switch_mm)
-#ifdef CONFIG_MMU
-       str     lr, [sp, #-4]!
-       bl      v4wb_flush_kern_cache_all       @ clears IP
+       flush_110_dcache        r3, ip, r1
+       mov     r1, #0
+       mcr     p15, 0, r1, c7, c5, 0           @ invalidate I cache
+       mcr     p15, 0, r1, c7, c10, 4          @ drain WB
        mcr     p15, 0, r0, c2, c0, 0           @ load page table pointer
-       mcr     p15, 0, ip, c8, c7, 0           @ invalidate I & D TLBs
-       ldr     pc, [sp], #4
-#else
+       mcr     p15, 0, r1, c8, c7, 0           @ invalidate I & D TLBs
        mov     pc, lr
-#endif
 
 /*
  * cpu_sa110_set_pte(ptep, pte)
@@ -152,7 +159,6 @@ ENTRY(cpu_sa110_switch_mm)
  */
        .align  5
 ENTRY(cpu_sa110_set_pte)
-#ifdef CONFIG_MMU
        str     r1, [r0], #-2048                @ linux version
 
        eor     r1, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY
@@ -174,7 +180,6 @@ ENTRY(cpu_sa110_set_pte)
        mov     r0, r0
        mcr     p15, 0, r0, c7, c10, 1          @ clean D entry
        mcr     p15, 0, r0, c7, c10, 4          @ drain WB
-#endif
        mov     pc, lr
 
        __INIT
@@ -184,15 +189,12 @@ __sa110_setup:
        mov     r10, #0
        mcr     p15, 0, r10, c7, c7             @ invalidate I,D caches on v4
        mcr     p15, 0, r10, c7, c10, 4         @ drain write buffer on v4
-#ifdef CONFIG_MMU
        mcr     p15, 0, r10, c8, c7             @ invalidate I,D TLBs on v4
-#endif
-
-       adr     r5, sa110_crval
-       ldmia   r5, {r5, r6}
        mrc     p15, 0, r0, c1, c0              @ get control register v4
+       ldr     r5, sa110_cr1_clear
        bic     r0, r0, r5
-       orr     r0, r0, r6
+       ldr     r5, sa110_cr1_set
+       orr     r0, r0, r5
        mov     pc, lr
        .size   __sa110_setup, . - __sa110_setup
 
@@ -202,9 +204,12 @@ __sa110_setup:
         * ..01 0001 ..11 1101
         * 
         */
-       .type   sa110_crval, #object
-sa110_crval:
-       crval   clear=0x00003f3f, mmuset=0x0000113d, ucset=0x00001130
+       .type   sa110_cr1_clear, #object
+       .type   sa110_cr1_set, #object
+sa110_cr1_clear:
+       .word   0x3f3f
+sa110_cr1_set:
+       .word   0x113d
 
        __INITDATA
 
@@ -255,9 +260,6 @@ __sa110_proc_info:
                PMD_SECT_CACHEABLE | \
                PMD_SECT_AP_WRITE | \
                PMD_SECT_AP_READ
-       .long   PMD_TYPE_SECT | \
-               PMD_SECT_AP_WRITE | \
-               PMD_SECT_AP_READ
        b       __sa110_setup
        .long   cpu_arch_name
        .long   cpu_elf_name