#include <linux/spinlock.h>
#include <linux/errno.h>
#include <linux/interrupt.h>
-#include <linux/irq.h>
#include <asm/system.h>
+#include <asm/irq.h>
#include <asm/hardware.h>
#include <asm/dma.h>
#include <asm/io.h>
#define OMAP_DMA_ACTIVE 0x01
#define OMAP_DMA_CCR_EN (1 << 7)
-#define OMAP2_DMA_CSR_CLEAR_MASK 0xffe
#define OMAP_FUNC_MUX_ARM_BASE (0xfffe1000 + 0xec)
if (cpu_is_omap24xx() && dma_trigger) {
u32 val = OMAP_DMA_CCR_REG(lch);
- val &= ~(3 << 19);
if (dma_trigger > 63)
val |= 1 << 20;
if (dma_trigger > 31)
val |= 1 << 19;
- val &= ~(0x1f);
val |= (dma_trigger & 0x1f);
if (sync_mode & OMAP_DMA_SYNC_FRAME)
val |= 1 << 5;
- else
- val &= ~(1 << 5);
if (sync_mode & OMAP_DMA_SYNC_BLOCK)
val |= 1 << 18;
- else
- val &= ~(1 << 18);
if (src_or_dst_synch)
val |= 1 << 24; /* source synch */
void omap_set_dma_src_burst_mode(int lch, enum omap_dma_burst_mode burst_mode)
{
- unsigned int burst = 0;
OMAP_DMA_CSDP_REG(lch) &= ~(0x03 << 7);
switch (burst_mode) {
case OMAP_DMA_DATA_BURST_DIS:
break;
case OMAP_DMA_DATA_BURST_4:
- if (cpu_is_omap24xx())
- burst = 0x1;
- else
- burst = 0x2;
+ OMAP_DMA_CSDP_REG(lch) |= (0x02 << 7);
break;
case OMAP_DMA_DATA_BURST_8:
- if (cpu_is_omap24xx()) {
- burst = 0x2;
- break;
- }
- /* not supported by current hardware on OMAP1
+ /* not supported by current hardware
* w |= (0x03 << 7);
* fall through
*/
- case OMAP_DMA_DATA_BURST_16:
- if (cpu_is_omap24xx()) {
- burst = 0x3;
- break;
- }
- /* OMAP1 don't support burst 16
- * fall through
- */
default:
BUG();
}
- OMAP_DMA_CSDP_REG(lch) |= (burst << 7);
}
/* Note that dest_port is only for OMAP1 */
void omap_set_dma_dest_burst_mode(int lch, enum omap_dma_burst_mode burst_mode)
{
- unsigned int burst = 0;
OMAP_DMA_CSDP_REG(lch) &= ~(0x03 << 14);
switch (burst_mode) {
case OMAP_DMA_DATA_BURST_DIS:
break;
case OMAP_DMA_DATA_BURST_4:
- if (cpu_is_omap24xx())
- burst = 0x1;
- else
- burst = 0x2;
+ OMAP_DMA_CSDP_REG(lch) |= (0x02 << 14);
break;
case OMAP_DMA_DATA_BURST_8:
- if (cpu_is_omap24xx())
- burst = 0x2;
- else
- burst = 0x3;
+ OMAP_DMA_CSDP_REG(lch) |= (0x03 << 14);
break;
- case OMAP_DMA_DATA_BURST_16:
- if (cpu_is_omap24xx()) {
- burst = 0x3;
- break;
- }
- /* OMAP1 don't support burst 16
- * fall through
- */
default:
printk(KERN_ERR "Invalid DMA burst mode\n");
BUG();
return;
}
- OMAP_DMA_CSDP_REG(lch) |= (burst << 14);
}
static inline void omap_enable_channel_irq(int lch)
{
u32 status;
- /* Clear CSR */
- if (cpu_class_is_omap1())
- status = OMAP_DMA_CSR_REG(lch);
- else if (cpu_is_omap24xx())
- OMAP_DMA_CSR_REG(lch) = OMAP2_DMA_CSR_CLEAR_MASK;
+ /* Read CSR to make sure it's cleared. */
+ status = OMAP_DMA_CSR_REG(lch);
/* Enable some nice interrupts. */
OMAP_DMA_CICR_REG(lch) = dma_chan[lch].enabled_irqs;
chan->dev_name = dev_name;
chan->callback = callback;
chan->data = data;
- chan->enabled_irqs = OMAP_DMA_DROP_IRQ | OMAP_DMA_BLOCK_IRQ;
+ chan->enabled_irqs = OMAP_DMA_TOUT_IRQ | OMAP_DMA_DROP_IRQ |
+ OMAP_DMA_BLOCK_IRQ;
- if (cpu_class_is_omap1())
- chan->enabled_irqs |= OMAP1_DMA_TOUT_IRQ;
- else if (cpu_is_omap24xx())
- chan->enabled_irqs |= OMAP2_DMA_MISALIGNED_ERR_IRQ |
- OMAP2_DMA_TRANS_ERR_IRQ;
+ if (cpu_is_omap24xx())
+ chan->enabled_irqs |= OMAP2_DMA_TRANS_ERR_IRQ;
if (cpu_is_omap16xx()) {
/* If the sync device is set, configure it dynamically. */
omap_enable_channel_irq(free_ch);
/* Clear the CSR register and IRQ status register */
- OMAP_DMA_CSR_REG(free_ch) = OMAP2_DMA_CSR_CLEAR_MASK;
+ OMAP_DMA_CSR_REG(free_ch) = 0x0;
omap_writel(~0x0, OMAP_DMA4_IRQSTATUS_L0);
}
omap_writel(val, OMAP_DMA4_IRQENABLE_L0);
/* Clear the CSR register and IRQ status register */
- OMAP_DMA_CSR_REG(lch) = OMAP2_DMA_CSR_CLEAR_MASK;
+ OMAP_DMA_CSR_REG(lch) = 0x0;
val = omap_readl(OMAP_DMA4_IRQSTATUS_L0);
val |= 1 << lch;
"%d (CSR %04x)\n", ch, csr);
return 0;
}
- if (unlikely(csr & OMAP1_DMA_TOUT_IRQ))
+ if (unlikely(csr & OMAP_DMA_TOUT_IRQ))
printk(KERN_WARNING "DMA timeout with device %d\n",
dma_chan[ch].dev_id);
if (unlikely(csr & OMAP_DMA_DROP_IRQ))
return 0;
if (unlikely(dma_chan[ch].dev_id == -1))
return 0;
+ /* REVISIT: According to 24xx TRM, there's no TOUT_IE */
+ if (unlikely(status & OMAP_DMA_TOUT_IRQ))
+ printk(KERN_INFO "DMA timeout with device %d\n",
+ dma_chan[ch].dev_id);
if (unlikely(status & OMAP_DMA_DROP_IRQ))
printk(KERN_INFO
"DMA synchronization event drop occurred with device "
"%d\n", dma_chan[ch].dev_id);
+
if (unlikely(status & OMAP2_DMA_TRANS_ERR_IRQ))
printk(KERN_INFO "DMA transaction error with device %d\n",
dma_chan[ch].dev_id);
- if (unlikely(status & OMAP2_DMA_SECURE_ERR_IRQ))
- printk(KERN_INFO "DMA secure error with device %d\n",
- dma_chan[ch].dev_id);
- if (unlikely(status & OMAP2_DMA_MISALIGNED_ERR_IRQ))
- printk(KERN_INFO "DMA misaligned error with device %d\n",
- dma_chan[ch].dev_id);
- OMAP_DMA_CSR_REG(ch) = OMAP2_DMA_CSR_CLEAR_MASK;
+ OMAP_DMA_CSR_REG(ch) = 0x20;
val = omap_readl(OMAP_DMA4_IRQSTATUS_L0);
/* ch in this function is from 0-31 while in register it is 1-32 */
static struct irqaction omap24xx_dma_irq = {
.name = "DMA",
.handler = omap2_dma_irq_handler,
- .flags = IRQF_DISABLED
+ .flags = SA_INTERRUPT
};
#else
omap_writew(w, OMAP1610_DMA_LCD_CTRL);
}
-int omap_lcd_dma_ext_running(void)
-{
- return lcd_dma.ext_ctrl && lcd_dma.active;
-}
-
/*----------------------------------------------------------------------------*/
static int __init omap_init_dma(void)
EXPORT_SYMBOL(omap_enable_lcd_dma);
EXPORT_SYMBOL(omap_setup_lcd_dma);
EXPORT_SYMBOL(omap_stop_lcd_dma);
-EXPORT_SYMBOL(omap_lcd_dma_ext_running);
EXPORT_SYMBOL(omap_set_lcd_dma_b1);
EXPORT_SYMBOL(omap_set_lcd_dma_single_transfer);
EXPORT_SYMBOL(omap_set_lcd_dma_ext_controller);
git://git.onelab.eu / linux-2.6.git / blobdiff