#include <asm/i8259.h>
#include <asm/irq_cpu.h>
#include <asm/gt64120.h>
-#include <asm/ptrace.h>
#include <asm/mach-cobalt/cobalt.h>
-extern void cobalt_handle_int(void);
-
/*
* We have two types of interrupts that we handle, ones that come in through
* the CPU interrupt lines, and ones that come in on the via chip. The CPU
* 15 - IDE1
*/
-static inline void galileo_irq(struct pt_regs *regs)
+static inline void galileo_irq(void)
{
unsigned int mask, pending, devfn;
- mask = GALILEO_INL(GT_INTRMASK_OFS);
- pending = GALILEO_INL(GT_INTRCAUSE_OFS) & mask;
-
- if (pending & GALILEO_INTR_T0EXP) {
-
- GALILEO_OUTL(~GALILEO_INTR_T0EXP, GT_INTRCAUSE_OFS);
- do_IRQ(COBALT_GALILEO_IRQ, regs);
-
- } else if (pending & GALILEO_INTR_RETRY_CTR) {
-
- devfn = GALILEO_INL(GT_PCI0_CFGADDR_OFS) >> 8;
- GALILEO_OUTL(~GALILEO_INTR_RETRY_CTR, GT_INTRCAUSE_OFS);
- printk(KERN_WARNING "Galileo: PCI retry count exceeded (%02x.%u)\n",
- PCI_SLOT(devfn), PCI_FUNC(devfn));
-
+ mask = GT_READ(GT_INTRMASK_OFS);
+ pending = GT_READ(GT_INTRCAUSE_OFS) & mask;
+
+ if (pending & GT_INTR_T0EXP_MSK) {
+ GT_WRITE(GT_INTRCAUSE_OFS, ~GT_INTR_T0EXP_MSK);
+ do_IRQ(COBALT_GALILEO_IRQ);
+ } else if (pending & GT_INTR_RETRYCTR0_MSK) {
+ devfn = GT_READ(GT_PCI0_CFGADDR_OFS) >> 8;
+ GT_WRITE(GT_INTRCAUSE_OFS, ~GT_INTR_RETRYCTR0_MSK);
+ printk(KERN_WARNING
+ "Galileo: PCI retry count exceeded (%02x.%u)\n",
+ PCI_SLOT(devfn), PCI_FUNC(devfn));
} else {
-
- GALILEO_OUTL(mask & ~pending, GT_INTRMASK_OFS);
- printk(KERN_WARNING "Galileo: masking unexpected interrupt %08x\n", pending);
+ GT_WRITE(GT_INTRMASK_OFS, mask & ~pending);
+ printk(KERN_WARNING
+ "Galileo: masking unexpected interrupt %08x\n", pending);
}
}
-static inline void via_pic_irq(struct pt_regs *regs)
+static inline void via_pic_irq(void)
{
int irq;
irq = i8259_irq();
if (irq >= 0)
- do_IRQ(irq, regs);
+ do_IRQ(irq);
}
-asmlinkage void cobalt_irq(struct pt_regs *regs)
+asmlinkage void plat_irq_dispatch(void)
{
- unsigned pending;
-
- pending = read_c0_status() & read_c0_cause();
-
- if (pending & CAUSEF_IP2) /* COBALT_GALILEO_IRQ (18) */
-
- galileo_irq(regs);
-
- else if (pending & CAUSEF_IP6) /* COBALT_VIA_IRQ (22) */
-
- via_pic_irq(regs);
-
- else if (pending & CAUSEF_IP3) /* COBALT_ETH0_IRQ (19) */
-
- do_IRQ(COBALT_CPU_IRQ + 3, regs);
-
- else if (pending & CAUSEF_IP4) /* COBALT_ETH1_IRQ (20) */
-
- do_IRQ(COBALT_CPU_IRQ + 4, regs);
-
- else if (pending & CAUSEF_IP5) /* COBALT_SERIAL_IRQ (21) */
-
- do_IRQ(COBALT_CPU_IRQ + 5, regs);
-
- else if (pending & CAUSEF_IP7) /* IRQ 23 */
-
- do_IRQ(COBALT_CPU_IRQ + 7, regs);
+ unsigned pending = read_c0_status() & read_c0_cause();
+
+ if (pending & CAUSEF_IP2) /* COBALT_GALILEO_IRQ (18) */
+ galileo_irq();
+ else if (pending & CAUSEF_IP6) /* COBALT_VIA_IRQ (22) */
+ via_pic_irq();
+ else if (pending & CAUSEF_IP3) /* COBALT_ETH0_IRQ (19) */
+ do_IRQ(COBALT_CPU_IRQ + 3);
+ else if (pending & CAUSEF_IP4) /* COBALT_ETH1_IRQ (20) */
+ do_IRQ(COBALT_CPU_IRQ + 4);
+ else if (pending & CAUSEF_IP5) /* COBALT_SERIAL_IRQ (21) */
+ do_IRQ(COBALT_CPU_IRQ + 5);
+ else if (pending & CAUSEF_IP7) /* IRQ 23 */
+ do_IRQ(COBALT_CPU_IRQ + 7);
}
static struct irqaction irq_via = {
* Mask all Galileo interrupts. The Galileo
* handler is set in cobalt_timer_setup()
*/
- GALILEO_OUTL(0, GT_INTRMASK_OFS);
-
- set_except_vector(0, cobalt_handle_int);
+ GT_WRITE(GT_INTRMASK_OFS, 0);
init_i8259_irqs(); /* 0 ... 15 */
mips_cpu_irq_init(COBALT_CPU_IRQ); /* 16 ... 23 */