#include <asm/system.h>
#include <asm/gt64120.h>
-asmlinkage void plat_irq_dispatch(struct pt_regs *regs)
+asmlinkage inline void pci_intA(struct pt_regs *regs)
{
- unsigned int pending = read_c0_status() & read_c0_cause();
-
- if (pending & STATUSF_IP4) /* int2 hardware line (timer) */
- do_IRQ(4, regs);
- else if (pending & STATUSF_IP2) /* int0 hardware line */
- do_IRQ(GT_INTA, regs);
- else if (pending & STATUSF_IP5) /* int3 hardware line */
- do_IRQ(GT_INTD, regs);
- else if (pending & STATUSF_IP6) /* int4 hardware line */
- do_IRQ(6, regs);
- else if (pending & STATUSF_IP7) /* compare int */
- do_IRQ(7, regs);
- else
- spurious_interrupt(regs);
+ do_IRQ(GT_INTA, regs);
+}
+
+asmlinkage inline void pci_intD(struct pt_regs *regs)
+{
+ do_IRQ(GT_INTD, regs);
}
static void disable_ev64120_irq(unsigned int irq_nr)
enable_ev64120_irq(irq);
}
-static struct irq_chip ev64120_irq_type = {
+static struct hw_interrupt_type ev64120_irq_type = {
.typename = "EV64120",
.startup = startup_ev64120_irq,
.shutdown = shutdown_ev64120_irq,
void gt64120_irq_setup(void)
{
+ extern asmlinkage void galileo_handle_int(void);
+
/*
* Clear all of the interrupts while we change the able around a bit.
*/
clear_c0_status(ST0_IM);
+ /* Sets the exception_handler array. */
+ set_except_vector(0, galileo_handle_int);
+
local_irq_disable();
/*
/* Let's initialize our IRQ descriptors */
for (i = 0; i < NR_IRQS; i++) {
irq_desc[i].status = 0;
- irq_desc[i].chip = &no_irq_chip;
+ irq_desc[i].handler = &no_irq_type;
irq_desc[i].action = NULL;
irq_desc[i].depth = 0;
spin_lock_init(&irq_desc[i].lock);