linux 2.6.16.38 w/ vs2.0.3-rc1

[linux-2.6.git] / arch / mips / kernel / cpu-probe.c

diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
index aa2caa6..292f8b2 100644 (file)
--- a/arch/mips/kernel/cpu-probe.c
+++ b/arch/mips/kernel/cpu-probe.c
@@ -11,6 +11,7 @@
  * as published by the Free Software Foundation; either version
  * 2 of the License, or (at your option) any later version.
  */
+#include <linux/config.h>
 #include <linux/init.h>
 #include <linux/kernel.h>
 #include <linux/ptrace.h>
@@ -120,7 +121,6 @@ static inline void check_wait(void)
        case CPU_24K:
        case CPU_25KF:
        case CPU_34K:
-       case CPU_74K:
        case CPU_PR4450:
                cpu_wait = r4k_wait;
                printk(" available.\n");
@@ -291,7 +291,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c)
                 * for documentation.  Commented out because it shares
                 * it's c0_prid id number with the TX3900.
                 */
-               c->cputype = CPU_R4650;
+               c->cputype = CPU_R4650;
                c->isa_level = MIPS_CPU_ISA_III;
                c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_LLSC;
                c->tlbsize = 48;
@@ -432,15 +432,6 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c)
                             MIPS_CPU_LLSC;
                c->tlbsize = 64;
                break;
-       case PRID_IMP_R14000:
-               c->cputype = CPU_R14000;
-               c->isa_level = MIPS_CPU_ISA_IV;
-               c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
-                            MIPS_CPU_FPU | MIPS_CPU_32FPR |
-                            MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
-                            MIPS_CPU_LLSC;
-               c->tlbsize = 64;
-               break;
        }
 }
 
@@ -459,7 +450,7 @@ static inline unsigned int decode_config0(struct cpuinfo_mips *c)
        isa = (config0 & MIPS_CONF_AT) >> 13;
        switch (isa) {
        case 0:
-               switch ((config0 & MIPS_CONF_AR) >> 10) {
+               switch ((config0 >> 10) & 7) {
                case 0:
                        c->isa_level = MIPS_CPU_ISA_M32R1;
                        break;
@@ -471,7 +462,7 @@ static inline unsigned int decode_config0(struct cpuinfo_mips *c)
                }
                break;
        case 2:
-               switch ((config0 & MIPS_CONF_AR) >> 10) {
+               switch ((config0 >> 10) & 7) {
                case 0:
                        c->isa_level = MIPS_CPU_ISA_M64R1;
                        break;
@@ -548,7 +539,7 @@ static inline unsigned int decode_config3(struct cpuinfo_mips *c)
        return config3 & MIPS_CONF_M;
 }
 
-static void __init decode_configs(struct cpuinfo_mips *c)
+static inline void decode_configs(struct cpuinfo_mips *c)
 {
        /* MIPS32 or MIPS64 compliant CPU.  */
        c->options = MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE | MIPS_CPU_COUNTER |
@@ -596,13 +587,12 @@ static inline void cpu_probe_mips(struct cpuinfo_mips *c)
                break;
        case PRID_IMP_25KF:
                c->cputype = CPU_25KF;
+               /* Probe for L2 cache */
+               c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT;
                break;
        case PRID_IMP_34K:
                c->cputype = CPU_34K;
                break;
-       case PRID_IMP_74K:
-               c->cputype = CPU_74K;
-               break;
        }
 }
 
@@ -614,7 +604,7 @@ static inline void cpu_probe_alchemy(struct cpuinfo_mips *c)
        case PRID_IMP_AU1_REV2:
                switch ((c->processor_id >> 24) & 0xff) {
                case 0:
-                       c->cputype = CPU_AU1000;
+                       c->cputype = CPU_AU1000;
                        break;
                case 1:
                        c->cputype = CPU_AU1500;
@@ -652,7 +642,7 @@ static inline void cpu_probe_sibyte(struct cpuinfo_mips *c)
        case PRID_IMP_SB1:
                c->cputype = CPU_SB1;
                /* FPU in pass1 is known to have issues. */
-               if ((c->processor_id & 0xff) < 0x02)
+               if ((c->processor_id & 0xff) < 0x20)
                        c->options &= ~(MIPS_CPU_FPU | MIPS_CPU_32FPR);
                break;
        case PRID_IMP_SB1A:
@@ -715,7 +705,7 @@ __init void cpu_probe(void)
                break;
        case PRID_COMP_PHILIPS:
                cpu_probe_philips(c);
-               break;
+               break;
        default:
                c->cputype = CPU_UNKNOWN;
        }