VServer 1.9.2 (patch-2.6.8.1-vs1.9.2.diff)

[linux-2.6.git] / arch / mips / kernel / cpu-probe.c

diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
index 5013599..3677747 100644 (file)
--- a/arch/mips/kernel/cpu-probe.c
+++ b/arch/mips/kernel/cpu-probe.c
@@ -1,6 +1,8 @@
 /*
  * Processor capabilities determination functions.
  *
+ * Copyright (C) xxxx  the Anonymous
+ * Copyright (C) 2003  Maciej W. Rozycki
  * Copyright (C) 1994 - 2003 Ralf Baechle
  * Copyright (C) 2001 MIPS Inc.
  *
@@ -49,6 +51,14 @@ static void r4k_wait(void)
                ".set\tmips0");
 }
 
+/*
+ * The Au1xxx wait is available only if we run CONFIG_PM and
+ * the timer setup found we had a 32KHz counter available.
+ * There are still problems with functions that may call au1k_wait
+ * directly, but that will be discovered pretty quickly.
+ */
+extern void (*au1k_wait_ptr)(void);
+
 void au1k_wait(void)
 {
 #ifdef CONFIG_PM
@@ -90,7 +100,6 @@ static inline void check_wait(void)
        case CPU_R5000:
        case CPU_NEVADA:
        case CPU_RM7000:
-/*     case CPU_RM9000: */
        case CPU_TX49XX:
        case CPU_4KC:
        case CPU_4KEC:
@@ -102,12 +111,19 @@ static inline void check_wait(void)
                cpu_wait = r4k_wait;
                printk(" available.\n");
                break;
+#ifdef CONFIG_PM
        case CPU_AU1000:
        case CPU_AU1100:
        case CPU_AU1500:
-               cpu_wait = au1k_wait;
-               printk(" available.\n");
+               if (au1k_wait_ptr != NULL) {
+                       cpu_wait = au1k_wait_ptr;
+                       printk(" available.\n");
+               }
+               else {
+                       printk(" unavailable.\n");
+               }
                break;
+#endif
        default:
                printk(" unavailable.\n");
                break;
@@ -238,8 +254,8 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c)
                        break;
                default:
                        printk(KERN_INFO "Unexpected CPU of NEC VR4100 series\n");
-                               c->cputype = CPU_VR41XX;
-                               break;
+                       c->cputype = CPU_VR41XX;
+                       break;
                }
                c->isa_level = MIPS_CPU_ISA_III;
                c->options = R4K_OPTS;
@@ -371,7 +387,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c)
                c->cputype = CPU_RM9000;
                c->isa_level = MIPS_CPU_ISA_IV;
                c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
-                            MIPS_CPU_LLSC;
+                            MIPS_CPU_LLSC;
                /*
                 * Bit 29 in the info register of the RM9000
                 * indicates if the TLB has 48 or 64 entries.
@@ -407,9 +423,6 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c)
                             MIPS_CPU_LLSC;
                c->tlbsize = 64;
                break;
-       default:
-               c->cputype = CPU_UNKNOWN;
-               break;
        }
 }
 
@@ -475,9 +488,6 @@ static inline void cpu_probe_mips(struct cpuinfo_mips *c)
                /* Probe for L2 cache */
                c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT;
                break;
-       default:
-               c->cputype = CPU_UNKNOWN;
-               break;
        }
 }
 
@@ -505,9 +515,6 @@ static inline void cpu_probe_alchemy(struct cpuinfo_mips *c)
                        break;
                }
                c->isa_level = MIPS_CPU_ISA_M32;
-               break;
-       default:
-               c->cputype = CPU_UNKNOWN;
                break;
        }
 }
@@ -528,9 +535,6 @@ static inline void cpu_probe_sibyte(struct cpuinfo_mips *c)
                c->options |= MIPS_CPU_FPU | MIPS_CPU_32FPR;
 #endif
                break;
-       default:
-               c->cputype = CPU_UNKNOWN;
-               break;
        }
 }
 
@@ -542,14 +546,11 @@ static inline void cpu_probe_sandcraft(struct cpuinfo_mips *c)
                c->cputype = CPU_SR71000;
                c->isa_level = MIPS_CPU_ISA_M64;
                c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
-                                    MIPS_CPU_4KTLB | MIPS_CPU_FPU |
+                            MIPS_CPU_4KTLB | MIPS_CPU_FPU |
                             MIPS_CPU_COUNTER | MIPS_CPU_MCHECK;
                c->scache.ways = 8;
                c->tlbsize = 64;
                break;
-       default:
-               c->cputype = CPU_UNKNOWN;
-               break;
        }
 }
 
@@ -563,7 +564,6 @@ __init void cpu_probe(void)
 
        c->processor_id = read_c0_prid();
        switch (c->processor_id & 0xff0000) {
-
        case PRID_COMP_LEGACY:
                cpu_probe_legacy(c);
                break;