This commit was manufactured by cvs2svn to create tag

[linux-2.6.git] / arch / mips / kernel / cpu-probe.c

diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
index 3677747..5013599 100644 (file)
--- a/arch/mips/kernel/cpu-probe.c
+++ b/arch/mips/kernel/cpu-probe.c
@@ -1,8 +1,6 @@
 /*
  * Processor capabilities determination functions.
  *
- * Copyright (C) xxxx  the Anonymous
- * Copyright (C) 2003  Maciej W. Rozycki
  * Copyright (C) 1994 - 2003 Ralf Baechle
  * Copyright (C) 2001 MIPS Inc.
  *
@@ -51,14 +49,6 @@ static void r4k_wait(void)
                ".set\tmips0");
 }
 
-/*
- * The Au1xxx wait is available only if we run CONFIG_PM and
- * the timer setup found we had a 32KHz counter available.
- * There are still problems with functions that may call au1k_wait
- * directly, but that will be discovered pretty quickly.
- */
-extern void (*au1k_wait_ptr)(void);
-
 void au1k_wait(void)
 {
 #ifdef CONFIG_PM
@@ -100,6 +90,7 @@ static inline void check_wait(void)
        case CPU_R5000:
        case CPU_NEVADA:
        case CPU_RM7000:
+/*     case CPU_RM9000: */
        case CPU_TX49XX:
        case CPU_4KC:
        case CPU_4KEC:
@@ -111,19 +102,12 @@ static inline void check_wait(void)
                cpu_wait = r4k_wait;
                printk(" available.\n");
                break;
-#ifdef CONFIG_PM
        case CPU_AU1000:
        case CPU_AU1100:
        case CPU_AU1500:
-               if (au1k_wait_ptr != NULL) {
-                       cpu_wait = au1k_wait_ptr;
-                       printk(" available.\n");
-               }
-               else {
-                       printk(" unavailable.\n");
-               }
+               cpu_wait = au1k_wait;
+               printk(" available.\n");
                break;
-#endif
        default:
                printk(" unavailable.\n");
                break;
@@ -254,8 +238,8 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c)
                        break;
                default:
                        printk(KERN_INFO "Unexpected CPU of NEC VR4100 series\n");
-                       c->cputype = CPU_VR41XX;
-                       break;
+                               c->cputype = CPU_VR41XX;
+                               break;
                }
                c->isa_level = MIPS_CPU_ISA_III;
                c->options = R4K_OPTS;
@@ -387,7 +371,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c)
                c->cputype = CPU_RM9000;
                c->isa_level = MIPS_CPU_ISA_IV;
                c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
-                            MIPS_CPU_LLSC;
+                            MIPS_CPU_LLSC;
                /*
                 * Bit 29 in the info register of the RM9000
                 * indicates if the TLB has 48 or 64 entries.
@@ -423,6 +407,9 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c)
                             MIPS_CPU_LLSC;
                c->tlbsize = 64;
                break;
+       default:
+               c->cputype = CPU_UNKNOWN;
+               break;
        }
 }
 
@@ -488,6 +475,9 @@ static inline void cpu_probe_mips(struct cpuinfo_mips *c)
                /* Probe for L2 cache */
                c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT;
                break;
+       default:
+               c->cputype = CPU_UNKNOWN;
+               break;
        }
 }
 
@@ -515,6 +505,9 @@ static inline void cpu_probe_alchemy(struct cpuinfo_mips *c)
                        break;
                }
                c->isa_level = MIPS_CPU_ISA_M32;
+               break;
+       default:
+               c->cputype = CPU_UNKNOWN;
                break;
        }
 }
@@ -535,6 +528,9 @@ static inline void cpu_probe_sibyte(struct cpuinfo_mips *c)
                c->options |= MIPS_CPU_FPU | MIPS_CPU_32FPR;
 #endif
                break;
+       default:
+               c->cputype = CPU_UNKNOWN;
+               break;
        }
 }
 
@@ -546,11 +542,14 @@ static inline void cpu_probe_sandcraft(struct cpuinfo_mips *c)
                c->cputype = CPU_SR71000;
                c->isa_level = MIPS_CPU_ISA_M64;
                c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
-                            MIPS_CPU_4KTLB | MIPS_CPU_FPU |
+                                    MIPS_CPU_4KTLB | MIPS_CPU_FPU |
                             MIPS_CPU_COUNTER | MIPS_CPU_MCHECK;
                c->scache.ways = 8;
                c->tlbsize = 64;
                break;
+       default:
+               c->cputype = CPU_UNKNOWN;
+               break;
        }
 }
 
@@ -564,6 +563,7 @@ __init void cpu_probe(void)
 
        c->processor_id = read_c0_prid();
        switch (c->processor_id & 0xff0000) {
+
        case PRID_COMP_LEGACY:
                cpu_probe_legacy(c);
                break;