Fedora kernel-2.6.17-1.2142_FC4 patched with stable patch-2.6.17.4-vs2.0.2-rc26.diff

[linux-2.6.git] / arch / mips / kernel / irq_cpu.c

diff --git a/arch/mips/kernel/irq_cpu.c b/arch/mips/kernel/irq_cpu.c
index 2b936cf..5db67e3 100644 (file)
--- a/arch/mips/kernel/irq_cpu.c
+++ b/arch/mips/kernel/irq_cpu.c
@@ -3,6 +3,8 @@
  * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net
  *
  * Copyright (C) 2001 Ralf Baechle
+ * Copyright (C) 2005  MIPS Technologies, Inc.  All rights reserved.
+ *      Author: Maciej W. Rozycki <macro@mips.com>
  *
  * This file define the irq handler for MIPS CPU interrupts.
  *
@@ -31,19 +33,21 @@
 
 #include <asm/irq_cpu.h>
 #include <asm/mipsregs.h>
+#include <asm/mipsmtregs.h>
 #include <asm/system.h>
 
 static int mips_cpu_irq_base;
 
 static inline void unmask_mips_irq(unsigned int irq)
 {
-       clear_c0_cause(0x100 << (irq - mips_cpu_irq_base));
        set_c0_status(0x100 << (irq - mips_cpu_irq_base));
+       irq_enable_hazard();
 }
 
 static inline void mask_mips_irq(unsigned int irq)
 {
        clear_c0_status(0x100 << (irq - mips_cpu_irq_base));
+       irq_disable_hazard();
 }
 
 static inline void mips_cpu_irq_enable(unsigned int irq)
@@ -52,6 +56,7 @@ static inline void mips_cpu_irq_enable(unsigned int irq)
 
        local_irq_save(flags);
        unmask_mips_irq(irq);
+       back_to_back_c0_hazard();
        local_irq_restore(flags);
 }
 
@@ -61,6 +66,7 @@ static void mips_cpu_irq_disable(unsigned int irq)
 
        local_irq_save(flags);
        mask_mips_irq(irq);
+       back_to_back_c0_hazard();
        local_irq_restore(flags);
 }
 
@@ -71,7 +77,7 @@ static unsigned int mips_cpu_irq_startup(unsigned int irq)
        return 0;
 }
 
-#define        mips_cpu_irq_shutdown   mips_cpu_irq_disable
+#define        mips_cpu_irq_shutdown           mips_cpu_irq_disable
 
 /*
  * While we ack the interrupt interrupts are disabled and thus we don't need
@@ -79,9 +85,6 @@ static unsigned int mips_cpu_irq_startup(unsigned int irq)
  */
 static void mips_cpu_irq_ack(unsigned int irq)
 {
-       /* Only necessary for soft interrupts */
-       clear_c0_cause(0x100 << (irq - mips_cpu_irq_base));
-
        mask_mips_irq(irq);
 }
 
@@ -92,22 +95,82 @@ static void mips_cpu_irq_end(unsigned int irq)
 }
 
 static hw_irq_controller mips_cpu_irq_controller = {
-       "MIPS",
-       mips_cpu_irq_startup,
-       mips_cpu_irq_shutdown,
-       mips_cpu_irq_enable,
-       mips_cpu_irq_disable,
-       mips_cpu_irq_ack,
-       mips_cpu_irq_end,
-       NULL                    /* no affinity stuff for UP */
+       .typename       = "MIPS",
+       .startup        = mips_cpu_irq_startup,
+       .shutdown       = mips_cpu_irq_shutdown,
+       .enable         = mips_cpu_irq_enable,
+       .disable        = mips_cpu_irq_disable,
+       .ack            = mips_cpu_irq_ack,
+       .end            = mips_cpu_irq_end,
 };
 
+/*
+ * Basically the same as above but taking care of all the MT stuff
+ */
+
+#define unmask_mips_mt_irq     unmask_mips_irq
+#define mask_mips_mt_irq       mask_mips_irq
+#define mips_mt_cpu_irq_enable mips_cpu_irq_enable
+#define mips_mt_cpu_irq_disable        mips_cpu_irq_disable
+
+static unsigned int mips_mt_cpu_irq_startup(unsigned int irq)
+{
+       unsigned int vpflags = dvpe();
+
+       clear_c0_cause(0x100 << (irq - mips_cpu_irq_base));
+       evpe(vpflags);
+       mips_mt_cpu_irq_enable(irq);
+
+       return 0;
+}
+
+#define        mips_mt_cpu_irq_shutdown        mips_mt_cpu_irq_disable
+
+/*
+ * While we ack the interrupt interrupts are disabled and thus we don't need
+ * to deal with concurrency issues.  Same for mips_cpu_irq_end.
+ */
+static void mips_mt_cpu_irq_ack(unsigned int irq)
+{
+       unsigned int vpflags = dvpe();
+       clear_c0_cause(0x100 << (irq - mips_cpu_irq_base));
+       evpe(vpflags);
+       mask_mips_mt_irq(irq);
+}
+
+#define mips_mt_cpu_irq_end mips_cpu_irq_end
+
+static hw_irq_controller mips_mt_cpu_irq_controller = {
+       .typename       = "MIPS",
+       .startup        = mips_mt_cpu_irq_startup,
+       .shutdown       = mips_mt_cpu_irq_shutdown,
+       .enable         = mips_mt_cpu_irq_enable,
+       .disable        = mips_mt_cpu_irq_disable,
+       .ack            = mips_mt_cpu_irq_ack,
+       .end            = mips_mt_cpu_irq_end,
+};
 
 void __init mips_cpu_irq_init(int irq_base)
 {
        int i;
 
-       for (i = irq_base; i < irq_base + 8; i++) {
+       /* Mask interrupts. */
+       clear_c0_status(ST0_IM);
+       clear_c0_cause(CAUSEF_IP);
+
+       /*
+        * Only MT is using the software interrupts currently, so we just
+        * leave them uninitialized for other processors.
+        */
+       if (cpu_has_mipsmt)
+               for (i = irq_base; i < irq_base + 2; i++) {
+                       irq_desc[i].status = IRQ_DISABLED;
+                       irq_desc[i].action = NULL;
+                       irq_desc[i].depth = 1;
+                       irq_desc[i].handler = &mips_mt_cpu_irq_controller;
+               }
+
+       for (i = irq_base + 2; i < irq_base + 8; i++) {
                irq_desc[i].status = IRQ_DISABLED;
                irq_desc[i].action = NULL;
                irq_desc[i].depth = 1;