VServer 1.9.2 (patch-2.6.8.1-vs1.9.2.diff)

[linux-2.6.git] / arch / mips / mm / sc-rm7k.c

diff --git a/arch/mips/mm/sc-rm7k.c b/arch/mips/mm/sc-rm7k.c
index ec3ec9e..9796a22 100644 (file)
--- a/arch/mips/mm/sc-rm7k.c
+++ b/arch/mips/mm/sc-rm7k.c
@@ -147,55 +147,47 @@ static void rm7k_sc_disable(void)
        clear_c0_config(1<<3);                          /* CONF_SE */
 }
 
-static inline int __init rm7k_sc_probe(void)
+struct bcache_ops rm7k_sc_ops = {
+       .bc_enable = rm7k_sc_enable,
+       .bc_disable = rm7k_sc_disable,
+       .bc_wback_inv = rm7k_sc_wback_inv,
+       .bc_inv = rm7k_sc_inv
+};
+
+void __init rm7k_sc_init(void)
 {
        unsigned int config = read_c0_config();
 
-       if ((config >> 31) & 1)
-               return 0;
+       if ((config >> 31) & 1)         /* Bit 31 set -> no S-Cache */
+               return;
 
        printk(KERN_INFO "Secondary cache size %dK, linesize %d bytes.\n",
               (scache_size >> 10), sc_lsize);
 
-       if ((config >> 3) & 1)                          /* CONF_SE */
-               return 1;
+       if (!((config >> 3) & 1))       /* CONF_SE */
+               rm7k_sc_enable();
 
        /*
         * While we're at it let's deal with the tertiary cache.
         */
-       if ((config >> 17) & 1)
-               return 1;
-
-       /*
-        * We can't enable the L3 cache yet. There may be board-specific
-        * magic necessary to turn it on, and blindly asking the CPU to
-        * start using it would may give cache errors.
-        *
-        * Also, board-specific knowledge may allow us to use the
-        * CACHE Flash_Invalidate_T instruction if the tag RAM supports
-        * it, and may specify the size of the L3 cache so we don't have
-        * to probe it.
-        */
-       printk(KERN_INFO "Tertiary cache present, %s enabled\n",
-              config&(1<<12) ? "already" : "not (yet)");
-
-       if ((config >> 12) & 1)
-               rm7k_tcache_enabled = 1;
-
-       return 1;
-}
-
-struct bcache_ops rm7k_sc_ops = {
-       .bc_enable = rm7k_sc_enable,
-       .bc_disable = rm7k_sc_disable,
-       .bc_wback_inv = rm7k_sc_wback_inv,
-       .bc_inv = rm7k_sc_inv
-};
-
-void __init rm7k_sc_init(void)
-{
-       if (rm7k_sc_probe()) {
-               rm7k_sc_enable();
-               bcops = &rm7k_sc_ops;
+       if (!((config >> 17) & 1)) {
+
+               /*
+                * We can't enable the L3 cache yet. There may be board-specific
+                * magic necessary to turn it on, and blindly asking the CPU to
+                * start using it would may give cache errors.
+                *
+                * Also, board-specific knowledge may allow us to use the
+                * CACHE Flash_Invalidate_T instruction if the tag RAM supports
+                * it, and may specify the size of the L3 cache so we don't have
+                * to probe it.
+                */
+               printk(KERN_INFO "Tertiary cache present, %s enabled\n",
+                      config&(1<<12) ? "already" : "not (yet)");
+
+               if ((config >> 12) & 1)
+                       rm7k_tcache_enabled = 1;
        }
+
+       bcops = &rm7k_sc_ops;
 }