vserver 1.9.5.x5

[linux-2.6.git] / arch / mips / mm / tlb-r4k.c

diff --git a/arch/mips/mm/tlb-r4k.c b/arch/mips/mm/tlb-r4k.c
index 91fee06..59d38bc 100644 (file)
--- a/arch/mips/mm/tlb-r4k.c
+++ b/arch/mips/mm/tlb-r4k.c
@@ -19,12 +19,7 @@
 #include <asm/pgtable.h>
 #include <asm/system.h>
 
-extern void except_vec0_generic(void);
-extern void except_vec0_nevada(void);
-extern void except_vec0_r4000(void);
-extern void except_vec0_r4600(void);
-extern void except_vec1_generic(void);
-extern void except_vec1_r4k(void);
+extern void build_tlb_refill_handler(void);
 
 /* CP0 hazard avoidance. */
 #define BARRIER __asm__ __volatile__(".set noreorder\n\t" \
@@ -255,8 +250,14 @@ void __update_tlb(struct vm_area_struct * vma, unsigned long address, pte_t pte)
        idx = read_c0_index();
        ptep = pte_offset_map(pmdp, address);
 
-       write_c0_entrylo0(pte_val(*ptep++) >> 6);
-       write_c0_entrylo1(pte_val(*ptep) >> 6);
+ #if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32)
+       write_c0_entrylo0(ptep->pte_high);
+       ptep++;
+       write_c0_entrylo1(ptep->pte_high);
+#else
+       write_c0_entrylo0(pte_val(*ptep++) >> 6);
+       write_c0_entrylo1(pte_val(*ptep) >> 6);
+#endif
        write_c0_entryhi(address | pid);
        mtc0_tlbw_hazard();
        if (idx < 0)
@@ -414,19 +415,5 @@ void __init tlb_init(void)
        temp_tlb_entry = current_cpu_data.tlbsize - 1;
        local_flush_tlb_all();
 
-#ifdef CONFIG_MIPS32
-       if (current_cpu_data.cputype == CPU_NEVADA)
-               memcpy((void *)KSEG0, &except_vec0_nevada, 0x80);
-       else if (current_cpu_data.cputype == CPU_R4600)
-               memcpy((void *)KSEG0, &except_vec0_r4600, 0x80);
-       else
-               memcpy((void *)KSEG0, &except_vec0_r4000, 0x80);
-       memcpy((void *)(KSEG0 + 0x080), &except_vec1_generic, 0x80);
-       flush_icache_range(KSEG0, KSEG0 + 0x100);
-#endif
-#ifdef CONFIG_MIPS64
-       memcpy((void *)(CKSEG0 + 0x00), &except_vec0_generic, 0x80);
-       memcpy((void *)(CKSEG0 + 0x80), except_vec1_r4k, 0x80);
-       flush_icache_range(CKSEG0 + 0x80, CKSEG0 + 0x100);
-#endif
+       build_tlb_refill_handler();
 }