switch (size) {
case 1:
- *val = TITAN_READ_8(data_reg + (~reg & 0x3));
+ TITAN_READ_8(data_reg + (reg & 0x3), val);
break;
case 2:
- *val = TITAN_READ_16(data_reg + (~reg & 0x2));
+ TITAN_READ_16(data_reg + (reg & 0x2), val);
break;
case 4:
- *val = TITAN_READ(data_reg);
+ TITAN_READ(data_reg, val);
break;
}
/* write the data */
switch (size) {
case 1:
- TITAN_WRITE_8(data_reg + (~reg & 0x3), val);
+ TITAN_WRITE_8(data_reg + (reg & 0x3), val);
break;
case 2:
- TITAN_WRITE_16(data_reg + (~reg & 0x2), val);
+ TITAN_WRITE_16(data_reg + (reg & 0x2), val);
break;
case 4:
titan_read_config,
titan_write_config,
};
+
+void __init pcibios_init(void)
+{
+ /*
+ * XXX These values below need to change
+ */
+ ioport_resource.start = 0xe0000000;
+ ioport_resource.end = 0xe0000000 + 0x20000000 - 1;
+ iomem_resource.start = 0xc0000000;
+ iomem_resource.end = 0xc0000000 + 0x20000000 - 1;
+
+ pci_scan_bus(0, &titan_pci_ops, NULL);
+}