* 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
*
*/
-#include <linux/config.h>
#include <linux/init.h>
#include <linux/irq.h>
#include <linux/sched.h>
}
}
-static struct hw_interrupt_type level_irq_type = {
+static struct irq_chip level_irq_type = {
.typename = "PNX Level IRQ",
.startup = startup_irq,
.shutdown = shutdown_irq,
static struct irqaction gic_action = {
.handler = no_action,
- .flags = SA_INTERRUPT,
+ .flags = IRQF_DISABLED,
.name = "GIC",
};
static struct irqaction timer_action = {
.handler = no_action,
- .flags = SA_INTERRUPT,
+ .flags = IRQF_DISABLED,
.name = "Timer",
};
int configPR;
for (i = 0; i < PNX8550_INT_CP0_TOTINT; i++) {
- irq_desc[i].handler = &level_irq_type;
+ irq_desc[i].chip = &level_irq_type;
pnx8550_ack(i); /* mask the irq just in case */
}
/* mask/priority is still 0 so we will not get any
* interrupts until it is unmasked */
- irq_desc[i].handler = &level_irq_type;
+ irq_desc[i].chip = &level_irq_type;
}
/* Priority level 0 */
/* Set int vector table address */
PNX8550_GIC_VECTOR_0 = PNX8550_GIC_VECTOR_1 = 0;
- irq_desc[MIPS_CPU_GIC_IRQ].handler = &level_irq_type;
+ irq_desc[MIPS_CPU_GIC_IRQ].chip = &level_irq_type;
setup_irq(MIPS_CPU_GIC_IRQ, &gic_action);
/* init of Timer interrupts */
for (i = PNX8550_INT_TIMER_MIN; i <= PNX8550_INT_TIMER_MAX; i++) {
- irq_desc[i].handler = &level_irq_type;
+ irq_desc[i].chip = &level_irq_type;
}
/* Stop Timer 1-3 */
configPR |= 0x00000038;
write_c0_config7(configPR);
- irq_desc[MIPS_CPU_TIMER_IRQ].handler = &level_irq_type;
+ irq_desc[MIPS_CPU_TIMER_IRQ].chip = &level_irq_type;
setup_irq(MIPS_CPU_TIMER_IRQ, &timer_action);
}