fedora core 6 1.2949 + vserver 2.2.0

[linux-2.6.git] / arch / mips / sni / irq.c

diff --git a/arch/mips/sni/irq.c b/arch/mips/sni/irq.c
index 952038a..8511bcc 100644 (file)
--- a/arch/mips/sni/irq.c
+++ b/arch/mips/sni/irq.c
@@ -11,59 +11,37 @@
 #include <linux/interrupt.h>
 #include <linux/irq.h>
 #include <linux/kernel.h>
-#include <linux/spinlock.h>
 
 #include <asm/i8259.h>
 #include <asm/io.h>
 #include <asm/sni.h>
 
-DEFINE_SPINLOCK(pciasic_lock);
-
-extern asmlinkage void sni_rm200_pci_handle_int(void);
-
 static void enable_pciasic_irq(unsigned int irq)
 {
        unsigned int mask = 1 << (irq - PCIMT_IRQ_INT2);
-       unsigned long flags;
 
-       spin_lock_irqsave(&pciasic_lock, flags);
        *(volatile u8 *) PCIMT_IRQSEL |= mask;
-       spin_unlock_irqrestore(&pciasic_lock, flags);
-}
-
-static unsigned int startup_pciasic_irq(unsigned int irq)
-{
-       enable_pciasic_irq(irq);
-       return 0; /* never anything pending */
 }
 
-#define shutdown_pciasic_irq   disable_pciasic_irq
-
 void disable_pciasic_irq(unsigned int irq)
 {
        unsigned int mask = ~(1 << (irq - PCIMT_IRQ_INT2));
-       unsigned long flags;
 
-       spin_lock_irqsave(&pciasic_lock, flags);
        *(volatile u8 *) PCIMT_IRQSEL &= mask;
-       spin_unlock_irqrestore(&pciasic_lock, flags);
 }
 
-#define mask_and_ack_pciasic_irq disable_pciasic_irq
-
 static void end_pciasic_irq(unsigned int irq)
 {
        if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
                enable_pciasic_irq(irq);
 }
 
-static struct hw_interrupt_type pciasic_irq_type = {
+static struct irq_chip pciasic_irq_type = {
        .typename = "ASIC-PCI",
-       .startup = startup_pciasic_irq,
-       .shutdown = shutdown_pciasic_irq,
-       .enable = enable_pciasic_irq,
-       .disable = disable_pciasic_irq,
-       .ack = mask_and_ack_pciasic_irq,
+       .ack = disable_pciasic_irq,
+       .mask = disable_pciasic_irq,
+       .mask_ack = disable_pciasic_irq,
+       .unmask = enable_pciasic_irq,
        .end = end_pciasic_irq,
 };
 
@@ -71,20 +49,20 @@ static struct hw_interrupt_type pciasic_irq_type = {
  * hwint0 should deal with MP agent, ASIC PCI, EISA NMI and debug
  * button interrupts.  Later ...
  */
-void pciasic_hwint0(struct pt_regs *regs)
+static void pciasic_hwint0(void)
 {
        panic("Received int0 but no handler yet ...");
 }
 
 /* This interrupt was used for the com1 console on the first prototypes.  */
-void pciasic_hwint2(struct pt_regs *regs)
+static void pciasic_hwint2(void)
 {
        /* I think this shouldn't happen on production machines.  */
        panic("hwint2 and no handler yet");
 }
 
 /* hwint5 is the r4k count / compare interrupt  */
-void pciasic_hwint5(struct pt_regs *regs)
+static void pciasic_hwint5(void)
 {
        panic("hwint5 and no handler yet");
 }
@@ -105,7 +83,7 @@ static unsigned int ls1bit8(unsigned int x)
  *
  * The EISA_INT bit in CSITPEND is high active, all others are low active.
  */
-void pciasic_hwint1(struct pt_regs *regs)
+static void pciasic_hwint1(void)
 {
        u8 pend = *(volatile char *)PCIMT_CSITPEND;
        unsigned long flags;
@@ -121,13 +99,13 @@ void pciasic_hwint1(struct pt_regs *regs)
                if (unlikely(irq < 0))
                        return;
 
-               do_IRQ(irq, regs);
+               do_IRQ(irq);
        }
 
        if (!(pend & IT_SCSI)) {
                flags = read_c0_status();
                clear_c0_status(ST0_IM);
-               do_IRQ(PCIMT_IRQ_SCSI, regs);
+               do_IRQ(PCIMT_IRQ_SCSI);
                write_c0_status(flags);
        }
 }
@@ -135,7 +113,7 @@ void pciasic_hwint1(struct pt_regs *regs)
 /*
  * hwint 3 should deal with the PCI A - D interrupts,
  */
-void pciasic_hwint3(struct pt_regs *regs)
+static void pciasic_hwint3(void)
 {
        u8 pend = *(volatile char *)PCIMT_CSITPEND;
        int irq;
@@ -143,28 +121,45 @@ void pciasic_hwint3(struct pt_regs *regs)
        pend &= (IT_INTA | IT_INTB | IT_INTC | IT_INTD);
        clear_c0_status(IE_IRQ3);
        irq = PCIMT_IRQ_INT2 + ls1bit8(pend);
-       do_IRQ(irq, regs);
+       do_IRQ(irq);
        set_c0_status(IE_IRQ3);
 }
 
 /*
  * hwint 4 is used for only the onboard PCnet 32.
  */
-void pciasic_hwint4(struct pt_regs *regs)
+static void pciasic_hwint4(void)
 {
        clear_c0_status(IE_IRQ4);
-       do_IRQ(PCIMT_IRQ_ETHERNET, regs);
+       do_IRQ(PCIMT_IRQ_ETHERNET);
        set_c0_status(IE_IRQ4);
 }
 
-void __init init_pciasic(void)
+asmlinkage void plat_irq_dispatch(void)
 {
-       unsigned long flags;
+       unsigned int pending = read_c0_status() & read_c0_cause();
+       static unsigned char led_cache;
+
+       *(volatile unsigned char *) PCIMT_CSLED = ++led_cache;
+
+       if (pending & 0x0800)
+               pciasic_hwint1();
+       else if (pending & 0x4000)
+               pciasic_hwint4();
+       else if (pending & 0x2000)
+               pciasic_hwint3();
+       else if (pending & 0x1000)
+               pciasic_hwint2();
+       else if (pending & 0x8000)
+               pciasic_hwint5();
+       else if (pending & 0x0400)
+               pciasic_hwint0();
+}
 
-       spin_lock_irqsave(&pciasic_lock, flags);
+void __init init_pciasic(void)
+{
        * (volatile u8 *) PCIMT_IRQSEL =
                IT_EISA | IT_INTA | IT_INTB | IT_INTC | IT_INTD;
-       spin_unlock_irqrestore(&pciasic_lock, flags);
 }
 
 /*
@@ -176,18 +171,12 @@ void __init arch_init_irq(void)
 {
        int i;
 
-       set_except_vector(0, sni_rm200_pci_handle_int);
-
        init_i8259_irqs();                      /* Integrated i8259  */
        init_pciasic();
 
        /* Actually we've got more interrupts to handle ...  */
-       for (i = PCIMT_IRQ_INT2; i <= PCIMT_IRQ_ETHERNET; i++) {
-               irq_desc[i].status     = IRQ_DISABLED;
-               irq_desc[i].action     = 0;
-               irq_desc[i].depth      = 1;
-               irq_desc[i].handler    = &pciasic_irq_type;
-       }
+       for (i = PCIMT_IRQ_INT2; i <= PCIMT_IRQ_ETHERNET; i++)
+               set_irq_chip(i, &pciasic_irq_type);
 
        change_c0_status(ST0_IM, IE_IRQ1|IE_IRQ2|IE_IRQ3|IE_IRQ4);
 }