* - Added support for NEC VR4133.
* - Removed board_irq_init.
*/
+#include <linux/config.h>
#include <linux/errno.h>
#include <linux/init.h>
#include <linux/irq.h>
#include <linux/kernel.h>
+#include <linux/module.h>
#include <linux/smp.h>
#include <linux/types.h>
#define read_giuint(offset) readw(giu_base + (offset))
#define write_giuint(val, offset) writew((val), giu_base + (offset))
+#define GIUINT_HIGH_OFFSET 16
+
static inline uint16_t set_giuint(uint8_t offset, uint16_t set)
{
uint16_t res;
return res;
}
-void vr41xx_enable_giuint(int pin)
+static unsigned int startup_giuint_low_irq(unsigned int irq)
{
- if (pin < 16)
- set_giuint(GIUINTENL, (uint16_t)1 << pin);
- else
- set_giuint(GIUINTENH, (uint16_t)1 << (pin - 16));
+ unsigned int pin;
+
+ pin = GIU_IRQ_TO_PIN(irq);
+ write_giuint((uint16_t)1 << pin, GIUINTSTATL);
+ set_giuint(GIUINTENL, (uint16_t)1 << pin);
+
+ return 0;
}
-void vr41xx_disable_giuint(int pin)
+static void shutdown_giuint_low_irq(unsigned int irq)
{
- if (pin < 16)
- clear_giuint(GIUINTENL, (uint16_t)1 << pin);
- else
- clear_giuint(GIUINTENH, (uint16_t)1 << (pin - 16));
+ clear_giuint(GIUINTENL, (uint16_t)1 << GIU_IRQ_TO_PIN(irq));
}
-void vr41xx_clear_giuint(int pin)
+static void enable_giuint_low_irq(unsigned int irq)
{
- if (pin < 16)
- write_giuint((uint16_t)1 << pin, GIUINTSTATL);
- else
- write_giuint((uint16_t)1 << (pin - 16), GIUINTSTATH);
+ set_giuint(GIUINTENL, (uint16_t)1 << GIU_IRQ_TO_PIN(irq));
+}
+
+#define disable_giuint_low_irq shutdown_giuint_low_irq
+
+static void ack_giuint_low_irq(unsigned int irq)
+{
+ unsigned int pin;
+
+ pin = GIU_IRQ_TO_PIN(irq);
+ clear_giuint(GIUINTENL, (uint16_t)1 << pin);
+ write_giuint((uint16_t)1 << pin, GIUINTSTATL);
+}
+
+static void end_giuint_low_irq(unsigned int irq)
+{
+ if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
+ set_giuint(GIUINTENL, (uint16_t)1 << GIU_IRQ_TO_PIN(irq));
+}
+
+static struct hw_interrupt_type giuint_low_irq_type = {
+ .typename = "GIUINTL",
+ .startup = startup_giuint_low_irq,
+ .shutdown = shutdown_giuint_low_irq,
+ .enable = enable_giuint_low_irq,
+ .disable = disable_giuint_low_irq,
+ .ack = ack_giuint_low_irq,
+ .end = end_giuint_low_irq,
+};
+
+static unsigned int startup_giuint_high_irq(unsigned int irq)
+{
+ unsigned int pin;
+
+ pin = GIU_IRQ_TO_PIN(irq - GIUINT_HIGH_OFFSET);
+ write_giuint((uint16_t)1 << pin, GIUINTSTATH);
+ set_giuint(GIUINTENH, (uint16_t)1 << pin);
+
+ return 0;
+}
+
+static void shutdown_giuint_high_irq(unsigned int irq)
+{
+ clear_giuint(GIUINTENH, (uint16_t)1 << GIU_IRQ_TO_PIN(irq - GIUINT_HIGH_OFFSET));
+}
+
+static void enable_giuint_high_irq(unsigned int irq)
+{
+ set_giuint(GIUINTENH, (uint16_t)1 << GIU_IRQ_TO_PIN(irq - GIUINT_HIGH_OFFSET));
+}
+
+#define disable_giuint_high_irq shutdown_giuint_high_irq
+
+static void ack_giuint_high_irq(unsigned int irq)
+{
+ unsigned int pin;
+
+ pin = GIU_IRQ_TO_PIN(irq - GIUINT_HIGH_OFFSET);
+ clear_giuint(GIUINTENH, (uint16_t)1 << pin);
+ write_giuint((uint16_t)1 << pin, GIUINTSTATH);
+}
+
+static void end_giuint_high_irq(unsigned int irq)
+{
+ if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
+ set_giuint(GIUINTENH, (uint16_t)1 << GIU_IRQ_TO_PIN(irq - GIUINT_HIGH_OFFSET));
+}
+
+static struct hw_interrupt_type giuint_high_irq_type = {
+ .typename = "GIUINTH",
+ .startup = startup_giuint_high_irq,
+ .shutdown = shutdown_giuint_high_irq,
+ .enable = enable_giuint_high_irq,
+ .disable = disable_giuint_high_irq,
+ .ack = ack_giuint_high_irq,
+ .end = end_giuint_high_irq,
+};
+
+void __init init_vr41xx_giuint_irq(void)
+{
+ int i;
+
+ for (i = GIU_IRQ_BASE; i <= GIU_IRQ_LAST; i++) {
+ if (i < (GIU_IRQ_BASE + GIUINT_HIGH_OFFSET))
+ irq_desc[i].handler = &giuint_low_irq_type;
+ else
+ irq_desc[i].handler = &giuint_high_irq_type;
+ }
+
+ setup_irq(GIUINT_CASCADE_IRQ, &giu_cascade);
}
void vr41xx_set_irq_trigger(int pin, int trigger, int hold)
{
uint16_t mask;
- if (pin < 16) {
+ if (pin < GIUINT_HIGH_OFFSET) {
mask = (uint16_t)1 << pin;
if (trigger != TRIGGER_LEVEL) {
set_giuint(GIUINTTYPL, mask);
clear_giuint(GIUINTTYPL, mask);
clear_giuint(GIUINTHTSELL, mask);
}
+ write_giuint(mask, GIUINTSTATL);
} else {
- mask = (uint16_t)1 << (pin - 16);
+ mask = (uint16_t)1 << (pin - GIUINT_HIGH_OFFSET);
if (trigger != TRIGGER_LEVEL) {
set_giuint(GIUINTTYPH, mask);
if (hold == SIGNAL_HOLD)
clear_giuint(GIUINTTYPH, mask);
clear_giuint(GIUINTHTSELH, mask);
}
+ write_giuint(mask, GIUINTSTATH);
}
-
- vr41xx_clear_giuint(pin);
}
+EXPORT_SYMBOL(vr41xx_set_irq_trigger);
+
void vr41xx_set_irq_level(int pin, int level)
{
uint16_t mask;
- if (pin < 16) {
+ if (pin < GIUINT_HIGH_OFFSET) {
mask = (uint16_t)1 << pin;
if (level == LEVEL_HIGH)
set_giuint(GIUINTALSELL, mask);
else
clear_giuint(GIUINTALSELL, mask);
+ write_giuint(mask, GIUINTSTATL);
} else {
- mask = (uint16_t)1 << (pin - 16);
+ mask = (uint16_t)1 << (pin - GIUINT_HIGH_OFFSET);
if (level == LEVEL_HIGH)
set_giuint(GIUINTALSELH, mask);
else
clear_giuint(GIUINTALSELH, mask);
+ write_giuint(mask, GIUINTSTATH);
}
-
- vr41xx_clear_giuint(pin);
}
+EXPORT_SYMBOL(vr41xx_set_irq_level);
+
#define GIUINT_NR_IRQS 32
enum {
};
static struct vr41xx_giuint_cascade giuint_cascade[GIUINT_NR_IRQS];
-static struct irqaction giu_cascade = {no_action, 0, 0, "cascade", NULL, NULL};
+static struct irqaction giu_cascade = {no_action, 0, CPU_MASK_NONE, "cascade", NULL, NULL};
static int no_irq_number(int irq)
{
giuint_cascade[pin].get_irq_number = get_irq_number;
retval = setup_irq(irq, &giu_cascade);
- if (retval) {
+ if (retval != 0) {
giuint_cascade[pin].flag = GIUINT_NO_CASCADE;
giuint_cascade[pin].get_irq_number = no_irq_number;
}
return retval;
}
-unsigned int giuint_do_IRQ(int pin, struct pt_regs *regs)
+EXPORT_SYMBOL(vr41xx_cascade_irq);
+
+static inline int get_irq_pin_number(void)
+{
+ uint16_t pendl, pendh, maskl, maskh;
+ int i;
+
+ pendl = read_giuint(GIUINTSTATL);
+ pendh = read_giuint(GIUINTSTATH);
+ maskl = read_giuint(GIUINTENL);
+ maskh = read_giuint(GIUINTENH);
+
+ maskl &= pendl;
+ maskh &= pendh;
+
+ if (maskl) {
+ for (i = 0; i < 16; i++) {
+ if (maskl & ((uint16_t)1 << i))
+ return i;
+ }
+ } else if (maskh) {
+ for (i = 0; i < 16; i++) {
+ if (maskh & ((uint16_t)1 << i))
+ return i + GIUINT_HIGH_OFFSET;
+ }
+ }
+
+ printk(KERN_ERR "spurious GIU interrupt: %04x(%04x),%04x(%04x)\n",
+ maskl, pendl, maskh, pendh);
+
+ atomic_inc(&irq_err_count);
+
+ return -1;
+}
+
+static inline void ack_giuint_irq(int pin)
+{
+ if (pin < GIUINT_HIGH_OFFSET) {
+ clear_giuint(GIUINTENL, (uint16_t)1 << pin);
+ write_giuint((uint16_t)1 << pin, GIUINTSTATL);
+ } else {
+ pin -= GIUINT_HIGH_OFFSET;
+ clear_giuint(GIUINTENH, (uint16_t)1 << pin);
+ write_giuint((uint16_t)1 << pin, GIUINTSTATH);
+ }
+}
+
+static inline void end_giuint_irq(int pin)
+{
+ if (pin < GIUINT_HIGH_OFFSET)
+ set_giuint(GIUINTENL, (uint16_t)1 << pin);
+ else
+ set_giuint(GIUINTENH, (uint16_t)1 << (pin - GIUINT_HIGH_OFFSET));
+}
+
+void giuint_irq_dispatch(struct pt_regs *regs)
{
struct vr41xx_giuint_cascade *cascade;
- unsigned int retval = 0;
- int giuint_irq, cascade_irq;
+ unsigned int giuint_irq;
+ int pin;
+
+ pin = get_irq_pin_number();
+ if (pin < 0)
+ return;
disable_irq(GIUINT_CASCADE_IRQ);
+
cascade = &giuint_cascade[pin];
giuint_irq = GIU_IRQ(pin);
if (cascade->flag == GIUINT_CASCADE) {
- cascade_irq = cascade->get_irq_number(giuint_irq);
- disable_irq(giuint_irq);
- if (cascade_irq > 0)
- retval = do_IRQ(cascade_irq, regs);
- enable_irq(giuint_irq);
- } else
- retval = do_IRQ(giuint_irq, regs);
- enable_irq(GIUINT_CASCADE_IRQ);
+ int irq = cascade->get_irq_number(giuint_irq);
+ ack_giuint_irq(pin);
+ if (irq >= 0)
+ do_IRQ(irq, regs);
+ end_giuint_irq(pin);
+ } else {
+ do_IRQ(giuint_irq, regs);
+ }
- return retval;
+ enable_irq(GIUINT_CASCADE_IRQ);
}
-void __init vr41xx_giuint_init(void)
+static int __init vr41xx_giu_init(void)
{
int i;
giu_base = GIUIOSELL_TYPE2;
break;
default:
- panic("GIU: Unexpected CPU of NEC VR4100 series");
- break;
+ printk(KERN_ERR "GIU: Unexpected CPU of NEC VR4100 series\n");
+ return -EINVAL;
}
for (i = 0; i < GIUINT_NR_IRQS; i++) {
- vr41xx_disable_giuint(i);
+ if (i < GIUINT_HIGH_OFFSET)
+ clear_giuint(GIUINTENL, (uint16_t)1 << i);
+ else
+ clear_giuint(GIUINTENH, (uint16_t)1 << (i - GIUINT_HIGH_OFFSET));
giuint_cascade[i].flag = GIUINT_NO_CASCADE;
giuint_cascade[i].get_irq_number = no_irq_number;
}
- if (setup_irq(GIUINT_CASCADE_IRQ, &giu_cascade))
- printk("GIUINT: Can not cascade IRQ %d.\n", GIUINT_CASCADE_IRQ);
+ return 0;
}
+
+early_initcall(vr41xx_giu_init);
git://git.onelab.eu / linux-2.6.git / blobdiff