linux 2.6.16.38 w/ vs2.0.3-rc1

[linux-2.6.git] / arch / powerpc / mm / hash_low_64.S

diff --git a/arch/powerpc/mm/hash_low_64.S b/arch/powerpc/mm/hash_low_64.S
index 9bc0a9c..e0d02c4 100644 (file)
--- a/arch/powerpc/mm/hash_low_64.S
+++ b/arch/powerpc/mm/hash_low_64.S
@@ -10,6 +10,7 @@
  * described in the kernel's COPYING file.
  */
 
+#include <linux/config.h>
 #include <asm/reg.h>
 #include <asm/pgtable.h>
 #include <asm/mmu.h>
@@ -135,7 +136,6 @@ _GLOBAL(__hash_page_4K)
        and     r0,r0,r4                /* _PAGE_RW & _PAGE_DIRTY ->r0 bit 30*/
        andc    r0,r30,r0               /* r0 = pte & ~r0 */
        rlwimi  r3,r0,32-1,31,31        /* Insert result into PP lsb */
-       ori     r3,r3,HPTE_R_C          /* Always add "C" bit for perf. */
 
        /* We eventually do the icache sync here (maybe inline that
         * code rather than call a C function...) 
@@ -368,7 +368,6 @@ _GLOBAL(__hash_page_4K)
        rlwinm  r30,r4,32-9+7,31-7,31-7 /* _PAGE_RW -> _PAGE_DIRTY */
        or      r30,r30,r31
        ori     r30,r30,_PAGE_BUSY | _PAGE_ACCESSED | _PAGE_HASHPTE
-       oris    r30,r30,_PAGE_COMBO@h
        /* Write the linux PTE atomically (setting busy) */
        stdcx.  r30,0,r6
        bne-    1b
@@ -401,7 +400,6 @@ _GLOBAL(__hash_page_4K)
        and     r0,r0,r4                /* _PAGE_RW & _PAGE_DIRTY ->r0 bit 30*/
        andc    r0,r30,r0               /* r0 = pte & ~r0 */
        rlwimi  r3,r0,32-1,31,31        /* Insert result into PP lsb */
-       ori     r3,r3,HPTE_R_C          /* Always add "C" bit for perf. */
 
        /* We eventually do the icache sync here (maybe inline that
         * code rather than call a C function...)
@@ -428,14 +426,6 @@ END_FTR_SECTION(CPU_FTR_NOEXECUTE|CPU_FTR_COHERENT_ICACHE, CPU_FTR_NOEXECUTE)
        andi.   r0,r31,_PAGE_HASHPTE
        li      r26,0                   /* Default hidx */
        beq     htab_insert_pte
-
-       /*
-        * Check if the pte was already inserted into the hash table
-        * as a 64k HW page, and invalidate the 64k HPTE if so.
-        */
-       andis.  r0,r31,_PAGE_COMBO@h
-       beq     htab_inval_old_hpte
-
        ld      r6,STK_PARM(r6)(r1)
        ori     r26,r6,0x8000           /* Load the hidx mask */
        ld      r26,0(r26)
@@ -506,19 +496,6 @@ _GLOBAL(htab_call_hpte_remove)
        /* Try all again */
        b       htab_insert_pte
 
-       /*
-        * Call out to C code to invalidate an 64k HW HPTE that is
-        * useless now that the segment has been switched to 4k pages.
-        */
-htab_inval_old_hpte:
-       mr      r3,r29                  /* virtual addr */
-       mr      r4,r31                  /* PTE.pte */
-       li      r5,0                    /* PTE.hidx */
-       li      r6,MMU_PAGE_64K         /* psize */
-       ld      r7,STK_PARM(r8)(r1)     /* local */
-       bl      .flush_hash_page
-       b       htab_insert_pte
-       
 htab_bail_ok:
        li      r3,0
        b       htab_bail
@@ -659,12 +636,6 @@ _GLOBAL(__hash_page_64K)
         * is changing this PTE anyway and might hash it.
         */
        bne-    ht64_bail_ok
-BEGIN_FTR_SECTION
-       /* Check if PTE has the cache-inhibit bit set */
-       andi.   r0,r31,_PAGE_NO_CACHE
-       /* If so, bail out and refault as a 4k page */
-       bne-    ht64_bail_ok
-END_FTR_SECTION_IFCLR(CPU_FTR_CI_LARGE_PAGE)
        /* Prepare new PTE value (turn access RW into DIRTY, then
         * add BUSY,HASHPTE and ACCESSED)
         */
@@ -700,7 +671,6 @@ END_FTR_SECTION_IFCLR(CPU_FTR_CI_LARGE_PAGE)
        and     r0,r0,r4                /* _PAGE_RW & _PAGE_DIRTY ->r0 bit 30*/
        andc    r0,r30,r0               /* r0 = pte & ~r0 */
        rlwimi  r3,r0,32-1,31,31        /* Insert result into PP lsb */
-       ori     r3,r3,HPTE_R_C          /* Always add "C" bit for perf. */
 
        /* We eventually do the icache sync here (maybe inline that
         * code rather than call a C function...)