fedora core 6 1.2949 + vserver 2.2.0

[linux-2.6.git] / arch / powerpc / platforms / cell / spufs / hw_ops.c

diff --git a/arch/powerpc/platforms/cell/spufs/hw_ops.c b/arch/powerpc/platforms/cell/spufs/hw_ops.c
index 5445719..ae42e03 100644 (file)
--- a/arch/powerpc/platforms/cell/spufs/hw_ops.c
+++ b/arch/powerpc/platforms/cell/spufs/hw_ops.c
@@ -18,7 +18,6 @@
  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  */
 
-#include <linux/config.h>
 #include <linux/module.h>
 #include <linux/errno.h>
 #include <linux/sched.h>
@@ -32,6 +31,7 @@
 
 #include <asm/io.h>
 #include <asm/spu.h>
+#include <asm/spu_priv1.h>
 #include <asm/spu_csa.h>
 #include <asm/mmu_context.h>
 #include "spufs.h"
@@ -135,21 +135,11 @@ static int spu_hw_wbox_write(struct spu_context *ctx, u32 data)
        return ret;
 }
 
-static u32 spu_hw_signal1_read(struct spu_context *ctx)
-{
-       return in_be32(&ctx->spu->problem->signal_notify1);
-}
-
 static void spu_hw_signal1_write(struct spu_context *ctx, u32 data)
 {
        out_be32(&ctx->spu->problem->signal_notify1, data);
 }
 
-static u32 spu_hw_signal2_read(struct spu_context *ctx)
-{
-       return in_be32(&ctx->spu->problem->signal_notify1);
-}
-
 static void spu_hw_signal2_write(struct spu_context *ctx, u32 data)
 {
        out_be32(&ctx->spu->problem->signal_notify2, data);
@@ -217,19 +207,93 @@ static char *spu_hw_get_ls(struct spu_context *ctx)
        return ctx->spu->local_store;
 }
 
+static u32 spu_hw_runcntl_read(struct spu_context *ctx)
+{
+       return in_be32(&ctx->spu->problem->spu_runcntl_RW);
+}
+
 static void spu_hw_runcntl_write(struct spu_context *ctx, u32 val)
 {
-       eieio();
+       spin_lock_irq(&ctx->spu->register_lock);
+       if (val & SPU_RUNCNTL_ISOLATE)
+               out_be64(&ctx->spu->priv2->spu_privcntl_RW, 4LL);
        out_be32(&ctx->spu->problem->spu_runcntl_RW, val);
+       spin_unlock_irq(&ctx->spu->register_lock);
+}
+
+static void spu_hw_master_start(struct spu_context *ctx)
+{
+       struct spu *spu = ctx->spu;
+       u64 sr1;
+
+       spin_lock_irq(&spu->register_lock);
+       sr1 = spu_mfc_sr1_get(spu) | MFC_STATE1_MASTER_RUN_CONTROL_MASK;
+       spu_mfc_sr1_set(spu, sr1);
+       spin_unlock_irq(&spu->register_lock);
+}
+
+static void spu_hw_master_stop(struct spu_context *ctx)
+{
+       struct spu *spu = ctx->spu;
+       u64 sr1;
+
+       spin_lock_irq(&spu->register_lock);
+       sr1 = spu_mfc_sr1_get(spu) & ~MFC_STATE1_MASTER_RUN_CONTROL_MASK;
+       spu_mfc_sr1_set(spu, sr1);
+       spin_unlock_irq(&spu->register_lock);
 }
 
-static void spu_hw_runcntl_stop(struct spu_context *ctx)
+static int spu_hw_set_mfc_query(struct spu_context * ctx, u32 mask, u32 mode)
 {
+       struct spu_problem __iomem *prob = ctx->spu->problem;
+       int ret;
+
        spin_lock_irq(&ctx->spu->register_lock);
-       out_be32(&ctx->spu->problem->spu_runcntl_RW, SPU_RUNCNTL_STOP);
-       while (in_be32(&ctx->spu->problem->spu_status_R) & SPU_STATUS_RUNNING)
-               cpu_relax();
+       ret = -EAGAIN;
+       if (in_be32(&prob->dma_querytype_RW))
+               goto out;
+       ret = 0;
+       out_be32(&prob->dma_querymask_RW, mask);
+       out_be32(&prob->dma_querytype_RW, mode);
+out:
        spin_unlock_irq(&ctx->spu->register_lock);
+       return ret;
+}
+
+static u32 spu_hw_read_mfc_tagstatus(struct spu_context * ctx)
+{
+       return in_be32(&ctx->spu->problem->dma_tagstatus_R);
+}
+
+static u32 spu_hw_get_mfc_free_elements(struct spu_context *ctx)
+{
+       return in_be32(&ctx->spu->problem->dma_qstatus_R);
+}
+
+static int spu_hw_send_mfc_command(struct spu_context *ctx,
+                                       struct mfc_dma_command *cmd)
+{
+       u32 status;
+       struct spu_problem __iomem *prob = ctx->spu->problem;
+
+       spin_lock_irq(&ctx->spu->register_lock);
+       out_be32(&prob->mfc_lsa_W, cmd->lsa);
+       out_be64(&prob->mfc_ea_W, cmd->ea);
+       out_be32(&prob->mfc_union_W.by32.mfc_size_tag32,
+                               cmd->size << 16 | cmd->tag);
+       out_be32(&prob->mfc_union_W.by32.mfc_class_cmd32,
+                               cmd->class << 16 | cmd->cmd);
+       status = in_be32(&prob->mfc_union_W.by32.mfc_class_cmd32);
+       spin_unlock_irq(&ctx->spu->register_lock);
+
+       switch (status & 0xffff) {
+       case 0:
+               return 0;
+       case 2:
+               return -EAGAIN;
+       default:
+               return -EINVAL;
+       }
 }
 
 struct spu_context_ops spu_hw_ops = {
@@ -238,9 +302,7 @@ struct spu_context_ops spu_hw_ops = {
        .mbox_stat_poll = spu_hw_mbox_stat_poll,
        .ibox_read = spu_hw_ibox_read,
        .wbox_write = spu_hw_wbox_write,
-       .signal1_read = spu_hw_signal1_read,
        .signal1_write = spu_hw_signal1_write,
-       .signal2_read = spu_hw_signal2_read,
        .signal2_write = spu_hw_signal2_write,
        .signal1_type_set = spu_hw_signal1_type_set,
        .signal1_type_get = spu_hw_signal1_type_get,
@@ -250,6 +312,12 @@ struct spu_context_ops spu_hw_ops = {
        .npc_write = spu_hw_npc_write,
        .status_read = spu_hw_status_read,
        .get_ls = spu_hw_get_ls,
+       .runcntl_read = spu_hw_runcntl_read,
        .runcntl_write = spu_hw_runcntl_write,
-       .runcntl_stop = spu_hw_runcntl_stop,
+       .master_start = spu_hw_master_start,
+       .master_stop = spu_hw_master_stop,
+       .set_mfc_query = spu_hw_set_mfc_query,
+       .read_mfc_tagstatus = spu_hw_read_mfc_tagstatus,
+       .get_mfc_free_elements = spu_hw_get_mfc_free_elements,
+       .send_mfc_command = spu_hw_send_mfc_command,
 };