Fedora kernel-2.6.17-1.2142_FC4 patched with stable patch-2.6.17.4-vs2.0.2-rc26.diff

[linux-2.6.git] / arch / ppc / 8xx_io / enet.c

diff --git a/arch/ppc/8xx_io/enet.c b/arch/ppc/8xx_io/enet.c
index 4ea7158..ece6a9f 100644 (file)
--- a/arch/ppc/8xx_io/enet.c
+++ b/arch/ppc/8xx_io/enet.c
@@ -714,16 +714,24 @@ static int __init scc_enet_init(void)
        immap->im_ioport.iop_pcdat &= ~PC_ENET_LBK;     /* Disable Loopback */
 #endif /* PC_ENET_LBK */
 
-       /* Configure port C pins to enable CLSN and RENA.
+#ifdef PE_ENET_TCLK
+       /* Configure port E for TCLK and RCLK.
        */
-       immap->im_ioport.iop_pcpar &= ~(PC_ENET_CLSN | PC_ENET_RENA);
-       immap->im_ioport.iop_pcdir &= ~(PC_ENET_CLSN | PC_ENET_RENA);
-       immap->im_ioport.iop_pcso  |=  (PC_ENET_CLSN | PC_ENET_RENA);
-
+       cp->cp_pepar |=  (PE_ENET_TCLK | PE_ENET_RCLK);
+       cp->cp_pedir &= ~(PE_ENET_TCLK | PE_ENET_RCLK);
+       cp->cp_peso  &= ~(PE_ENET_TCLK | PE_ENET_RCLK);
+#else
        /* Configure port A for TCLK and RCLK.
        */
        immap->im_ioport.iop_papar |=  (PA_ENET_TCLK | PA_ENET_RCLK);
        immap->im_ioport.iop_padir &= ~(PA_ENET_TCLK | PA_ENET_RCLK);
+#endif
+
+       /* Configure port C pins to enable CLSN and RENA.
+       */
+       immap->im_ioport.iop_pcpar &= ~(PC_ENET_CLSN | PC_ENET_RENA);
+       immap->im_ioport.iop_pcdir &= ~(PC_ENET_CLSN | PC_ENET_RENA);
+       immap->im_ioport.iop_pcso  |=  (PC_ENET_CLSN | PC_ENET_RENA);
 
        /* Configure Serial Interface clock routing.
         * First, clear all SCC bits to zero, then set the ones we want.
@@ -896,14 +904,18 @@ static int __init scc_enet_init(void)
        /* It is now OK to enable the Ethernet transmitter.
         * Unfortunately, there are board implementation differences here.
         */
-#if   (!defined (PB_ENET_TENA) &&  defined (PC_ENET_TENA))
+#if   (!defined (PB_ENET_TENA) &&  defined (PC_ENET_TENA) && !defined (PE_ENET_TENA))
        immap->im_ioport.iop_pcpar |=  PC_ENET_TENA;
        immap->im_ioport.iop_pcdir &= ~PC_ENET_TENA;
-#elif ( defined (PB_ENET_TENA) && !defined (PC_ENET_TENA))
+#elif ( defined (PB_ENET_TENA) && !defined (PC_ENET_TENA) && !defined (PE_ENET_TENA))
        cp->cp_pbpar |= PB_ENET_TENA;
        cp->cp_pbdir |= PB_ENET_TENA;
+#elif ( !defined (PB_ENET_TENA) && !defined (PC_ENET_TENA) && defined (PE_ENET_TENA))
+       cp->cp_pepar |=  PE_ENET_TENA;
+       cp->cp_pedir &= ~PE_ENET_TENA;
+       cp->cp_peso  |=  PE_ENET_TENA;
 #else
-#error Configuration Error: define exactly ONE of PB_ENET_TENA, PC_ENET_TENA
+#error Configuration Error: define exactly ONE of PB_ENET_TENA, PC_ENET_TENA, PE_ENET_TENA
 #endif
 
 #if defined(CONFIG_RPXLITE) || defined(CONFIG_RPXCLASSIC)
@@ -936,6 +948,29 @@ static int __init scc_enet_init(void)
        *((volatile uint *)BCSR1) &= ~BCSR1_ETHEN;
 #endif
 
+#ifdef CONFIG_MPC885ADS
+
+       /* Deassert PHY reset and enable the PHY.
+        */
+       {
+               volatile uint __iomem *bcsr = ioremap(BCSR_ADDR, BCSR_SIZE);
+               uint tmp;
+
+               tmp = in_be32(bcsr + 1 /* BCSR1 */);
+               tmp |= BCSR1_ETHEN;
+               out_be32(bcsr + 1, tmp);
+               tmp = in_be32(bcsr + 4 /* BCSR4 */);
+               tmp |= BCSR4_ETH10_RST;
+               out_be32(bcsr + 4, tmp);
+               iounmap(bcsr);
+       }
+
+       /* On MPC885ADS SCC ethernet PHY defaults to the full duplex mode
+        * upon reset. SCC is set to half duplex by default. So this
+        * inconsistency should be better fixed by the software.
+        */
+#endif
+
        dev->base_addr = (unsigned long)ep;
 #if 0
        dev->name = "CPM_ENET";
@@ -969,3 +1004,4 @@ static int __init scc_enet_init(void)
 }
 
 module_init(scc_enet_init);
+