linux 2.6.16.38 w/ vs2.0.3-rc1

[linux-2.6.git] / arch / ppc / kernel / cpu_setup_6xx.S

diff --git a/arch/ppc/kernel/cpu_setup_6xx.S b/arch/ppc/kernel/cpu_setup_6xx.S
index 468721d..55ed771 100644 (file)
--- a/arch/ppc/kernel/cpu_setup_6xx.S
+++ b/arch/ppc/kernel/cpu_setup_6xx.S
@@ -12,14 +12,11 @@
 #include <linux/config.h>
 #include <asm/processor.h>
 #include <asm/page.h>
-#include <asm/ppc_asm.h>
 #include <asm/cputable.h>
 #include <asm/ppc_asm.h>
-#include <asm/offsets.h>
+#include <asm/asm-offsets.h>
 #include <asm/cache.h>
 
-_GLOBAL(__setup_cpu_601)
-       blr
 _GLOBAL(__setup_cpu_603)
        b       setup_common_caches
 _GLOBAL(__setup_cpu_604)
@@ -249,8 +246,11 @@ END_FTR_SECTION_IFSET(CPU_FTR_NO_DPM)
        sync
        isync
 
-       /* Enable L2 HW prefetch
+       /* Enable L2 HW prefetch, if L2 is enabled
         */
+       mfspr   r3,SPRN_L2CR
+       andis.  r3,r3,L2CR_L2E@h
+       beqlr
        mfspr   r3,SPRN_MSSCR0
        ori     r3,r3,3
        sync
@@ -290,10 +290,10 @@ _GLOBAL(__init_fpu_registers)
 #define CS_SIZE                32
 
        .data
-       .balign L1_CACHE_LINE_SIZE
+       .balign L1_CACHE_BYTES
 cpu_state_storage:
        .space  CS_SIZE
-       .balign L1_CACHE_LINE_SIZE,0
+       .balign L1_CACHE_BYTES,0
        .text
 
 /* Called in normal context to backup CPU 0 state. This
@@ -324,6 +324,7 @@ _GLOBAL(__save_cpu_setup)
        cmplwi  cr4,r3,0x8002   /* 7457 */
        cmplwi  cr5,r3,0x8003   /* 7447A */
        cmplwi  cr6,r3,0x7000   /* 750FX */
+       cmplwi  cr7,r3,0x8004   /* 7448 */
        /* cr1 is 7400 || 7410 */
        cror    4*cr1+eq,4*cr1+eq,4*cr2+eq
        /* cr0 is 74xx */
@@ -331,6 +332,7 @@ _GLOBAL(__save_cpu_setup)
        cror    4*cr0+eq,4*cr0+eq,4*cr4+eq
        cror    4*cr0+eq,4*cr0+eq,4*cr1+eq
        cror    4*cr0+eq,4*cr0+eq,4*cr5+eq
+       cror    4*cr0+eq,4*cr0+eq,4*cr7+eq
        bne     1f
        /* Backup 74xx specific regs */
        mfspr   r4,SPRN_MSSCR0
@@ -393,6 +395,7 @@ _GLOBAL(__restore_cpu_setup)
        cmplwi  cr4,r3,0x8002   /* 7457 */
        cmplwi  cr5,r3,0x8003   /* 7447A */
        cmplwi  cr6,r3,0x7000   /* 750FX */
+       cmplwi  cr7,r3,0x8004   /* 7448 */
        /* cr1 is 7400 || 7410 */
        cror    4*cr1+eq,4*cr1+eq,4*cr2+eq
        /* cr0 is 74xx */
@@ -400,6 +403,7 @@ _GLOBAL(__restore_cpu_setup)
        cror    4*cr0+eq,4*cr0+eq,4*cr4+eq
        cror    4*cr0+eq,4*cr0+eq,4*cr1+eq
        cror    4*cr0+eq,4*cr0+eq,4*cr5+eq
+       cror    4*cr0+eq,4*cr0+eq,4*cr7+eq
        bne     2f
        /* Restore 74xx specific regs */
        lwz     r4,CS_MSSCR0(r5)