vserver 2.0 rc7

[linux-2.6.git] / arch / ppc / kernel / cpu_setup_6xx.S

diff --git a/arch/ppc/kernel/cpu_setup_6xx.S b/arch/ppc/kernel/cpu_setup_6xx.S
index 9a4ee63..468721d 100644 (file)
--- a/arch/ppc/kernel/cpu_setup_6xx.S
+++ b/arch/ppc/kernel/cpu_setup_6xx.S
@@ -30,12 +30,14 @@ _GLOBAL(__setup_cpu_604)
        blr
 _GLOBAL(__setup_cpu_750)
        mflr    r4
+       bl      __init_fpu_registers
        bl      setup_common_caches
        bl      setup_750_7400_hid0
        mtlr    r4
        blr
 _GLOBAL(__setup_cpu_750cx)
        mflr    r4
+       bl      __init_fpu_registers
        bl      setup_common_caches
        bl      setup_750_7400_hid0
        bl      setup_750cx
@@ -43,6 +45,7 @@ _GLOBAL(__setup_cpu_750cx)
        blr
 _GLOBAL(__setup_cpu_750fx)
        mflr    r4
+       bl      __init_fpu_registers
        bl      setup_common_caches
        bl      setup_750_7400_hid0
        bl      setup_750fx
@@ -50,6 +53,7 @@ _GLOBAL(__setup_cpu_750fx)
        blr
 _GLOBAL(__setup_cpu_7400)
        mflr    r4
+       bl      __init_fpu_registers
        bl      setup_7400_workarounds
        bl      setup_common_caches
        bl      setup_750_7400_hid0
@@ -57,6 +61,7 @@ _GLOBAL(__setup_cpu_7400)
        blr
 _GLOBAL(__setup_cpu_7410)
        mflr    r4
+       bl      __init_fpu_registers
        bl      setup_7410_workarounds
        bl      setup_common_caches
        bl      setup_750_7400_hid0
@@ -73,16 +78,16 @@ _GLOBAL(__setup_cpu_745x)
 
 /* Enable caches for 603's, 604, 750 & 7400 */
 setup_common_caches:
-       mfspr   r11,HID0
+       mfspr   r11,SPRN_HID0
        andi.   r0,r11,HID0_DCE
        ori     r11,r11,HID0_ICE|HID0_DCE
        ori     r8,r11,HID0_ICFI
        bne     1f                      /* don't invalidate the D-cache */
        ori     r8,r8,HID0_DCI          /* unless it wasn't enabled */
 1:     sync
-       mtspr   HID0,r8                 /* enable and invalidate caches */
+       mtspr   SPRN_HID0,r8            /* enable and invalidate caches */
        sync
-       mtspr   HID0,r11                /* enable caches */
+       mtspr   SPRN_HID0,r11           /* enable caches */
        sync
        isync
        blr
@@ -91,13 +96,13 @@ setup_common_caches:
  * Enable superscalar execution & branch history table
  */
 setup_604_hid0:
-       mfspr   r11,HID0
+       mfspr   r11,SPRN_HID0
        ori     r11,r11,HID0_SIED|HID0_BHTE
        ori     r8,r11,HID0_BTCD
        sync
-       mtspr   HID0,r8         /* flush branch target address cache */
+       mtspr   SPRN_HID0,r8    /* flush branch target address cache */
        sync                    /* on 604e/604r */
-       mtspr   HID0,r11
+       mtspr   SPRN_HID0,r11
        sync
        isync
        blr
@@ -150,17 +155,21 @@ setup_7410_workarounds:
  * Clear Instruction cache throttling (ICTC)
  */
 setup_750_7400_hid0:
-       mfspr   r11,HID0
+       mfspr   r11,SPRN_HID0
        ori     r11,r11,HID0_SGE | HID0_ABE | HID0_BHTE | HID0_BTIC
+       oris    r11,r11,HID0_DPM@h
 BEGIN_FTR_SECTION
-       oris    r11,r11,HID0_DPM@h      /* enable dynamic power mgmt */
-END_FTR_SECTION_IFCLR(CPU_FTR_NO_DPM)
+       xori    r11,r11,HID0_BTIC
+END_FTR_SECTION_IFSET(CPU_FTR_NO_BTIC)
+BEGIN_FTR_SECTION
+       xoris   r11,r11,HID0_DPM@h      /* disable dynamic power mgmt */
+END_FTR_SECTION_IFSET(CPU_FTR_NO_DPM)
        li      r3,HID0_SPD
        andc    r11,r11,r3              /* clear SPD: enable speculative */
        li      r3,0
-       mtspr   ICTC,r3                 /* Instruction Cache Throttling off */
+       mtspr   SPRN_ICTC,r3            /* Instruction Cache Throttling off */
        isync
-       mtspr   HID0,r11
+       mtspr   SPRN_HID0,r11
        sync
        isync
        blr
@@ -214,17 +223,19 @@ setup_745x_specifics:
        andc    r6,r6,r7
        stw     r6,CPU_SPEC_FEATURES(r5)
 1:
-       mfspr   r11,HID0
+       mfspr   r11,SPRN_HID0
 
        /* All of the bits we have to set.....
         */
-       ori     r11,r11,HID0_SGE | HID0_FOLD | HID0_BHTE | HID0_LRSTK | HID0_BTIC
+       ori     r11,r11,HID0_SGE | HID0_FOLD | HID0_BHTE
+       ori     r11,r11,HID0_LRSTK | HID0_BTIC
+       oris    r11,r11,HID0_DPM@h
 BEGIN_FTR_SECTION
        xori    r11,r11,HID0_BTIC
 END_FTR_SECTION_IFSET(CPU_FTR_NO_BTIC)
 BEGIN_FTR_SECTION
-       oris    r11,r11,HID0_DPM@h      /* enable dynamic power mgmt */
-END_FTR_SECTION_IFCLR(CPU_FTR_NO_DPM)
+       xoris   r11,r11,HID0_DPM@h      /* disable dynamic power mgmt */
+END_FTR_SECTION_IFSET(CPU_FTR_NO_DPM)
 
        /* All of the bits we have to clear....
         */
@@ -232,9 +243,9 @@ END_FTR_SECTION_IFCLR(CPU_FTR_NO_DPM)
        andc    r11,r11,r3              /* clear SPD: enable speculative */
        li      r3,0
 
-       mtspr   ICTC,r3                 /* Instruction Cache Throttling off */
+       mtspr   SPRN_ICTC,r3            /* Instruction Cache Throttling off */
        isync
-       mtspr   HID0,r11
+       mtspr   SPRN_HID0,r11
        sync
        isync
 
@@ -248,6 +259,25 @@ END_FTR_SECTION_IFCLR(CPU_FTR_NO_DPM)
        isync
        blr
 
+/*
+ * Initialize the FPU registers. This is needed to work around an errata
+ * in some 750 cpus where using a not yet initialized FPU register after
+ * power on reset may hang the CPU
+ */
+_GLOBAL(__init_fpu_registers)
+       mfmsr   r10
+       ori     r11,r10,MSR_FP
+       mtmsr   r11
+       isync
+       addis   r9,r3,empty_zero_page@ha
+       addi    r9,r9,empty_zero_page@l
+       REST_32FPRS(0,r9)
+       sync
+       mtmsr   r10
+       isync
+       blr
+
+
 /* Definitions for the table use to save CPU states */
 #define CS_HID0                0
 #define CS_HID1                4
@@ -285,7 +315,7 @@ _GLOBAL(__save_cpu_setup)
        stw     r3,CS_HID0(r5)
 
        /* Now deal with CPU type dependent registers */
-       mfspr   r3,PVR
+       mfspr   r3,SPRN_PVR
        srwi    r3,r3,16
        cmplwi  cr0,r3,0x8000   /* 7450 */
        cmplwi  cr1,r3,0x000c   /* 7400 */
@@ -323,7 +353,7 @@ _GLOBAL(__save_cpu_setup)
        mfspr   r4,SPRN_HID1
        stw     r4,CS_HID1(r5)
        /* If rev 2.x, backup HID2 */
-       mfspr   r3,PVR
+       mfspr   r3,SPRN_PVR
        andi.   r3,r3,0xff00
        cmpwi   cr0,r3,0x0200
        bne     1f
@@ -354,7 +384,7 @@ _GLOBAL(__restore_cpu_setup)
        isync
 
        /* Now deal with CPU type dependent registers */
-       mfspr   r3,PVR
+       mfspr   r3,SPRN_PVR
        srwi    r3,r3,16
        cmplwi  cr0,r3,0x8000   /* 7450 */
        cmplwi  cr1,r3,0x000c   /* 7400 */
@@ -414,7 +444,7 @@ _GLOBAL(__restore_cpu_setup)
         * to PLL 0 on all
         */
        /* If rev 2.x, restore HID2 with low voltage bit cleared */
-       mfspr   r3,PVR
+       mfspr   r3,SPRN_PVR
        andi.   r3,r3,0xff00
        cmpwi   cr0,r3,0x0200
        bne     4f