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[linux-2.6.git] / arch / ppc / kernel / cputable.c

diff --git a/arch/ppc/kernel/cputable.c b/arch/ppc/kernel/cputable.c
index b60fa99..4f560f5 100644 (file)
--- a/arch/ppc/kernel/cputable.c
+++ b/arch/ppc/kernel/cputable.c
@@ -55,8 +55,7 @@ extern void __setup_cpu_generic(unsigned long offset, int cpu_nr, struct cpu_spe
 #endif
 
 /* We need to mark all pages as being coherent if we're SMP or we
- * have a 754x and an MPC107 host bridge.
- */
+ * have a 754x and an MPC107 host bridge. */
 #if defined(CONFIG_SMP) || defined(CONFIG_MPC10X_BRIDGE)
 #define CPU_FTR_COMMON                  CPU_FTR_NEED_COHERENT
 #else
@@ -264,7 +263,7 @@ struct cpu_spec     cpu_specs[] = {
        CPU_FTR_COMMON |
        CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
        CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
-       CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | CPU_FTR_NEED_COHERENT,
+       CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450,
        COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
        32, 32,
        __setup_cpu_745x
@@ -275,7 +274,7 @@ struct cpu_spec     cpu_specs[] = {
        CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_CAN_NAP |
        CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
        CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR |
-       CPU_FTR_L3_DISABLE_NAP | CPU_FTR_NEED_COHERENT,
+       CPU_FTR_L3_DISABLE_NAP,
        COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
        32, 32,
        __setup_cpu_745x
@@ -285,8 +284,7 @@ struct cpu_spec     cpu_specs[] = {
        CPU_FTR_COMMON |
        CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_CAN_NAP |
        CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
-       CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR |
-       CPU_FTR_NEED_COHERENT,
+       CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR,
        COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
        32, 32,
        __setup_cpu_745x
@@ -296,8 +294,7 @@ struct cpu_spec     cpu_specs[] = {
        CPU_FTR_COMMON |
        CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
        CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
-       CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | CPU_FTR_HAS_HIGH_BATS |
-       CPU_FTR_NEED_COHERENT,
+       CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | CPU_FTR_HAS_HIGH_BATS,
        COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
        32, 32,
        __setup_cpu_745x
@@ -308,7 +305,7 @@ struct cpu_spec     cpu_specs[] = {
        CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_CAN_NAP |
        CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
        CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR |
-       CPU_FTR_L3_DISABLE_NAP | CPU_FTR_NEED_COHERENT | CPU_FTR_HAS_HIGH_BATS,
+       CPU_FTR_L3_DISABLE_NAP | CPU_FTR_HAS_HIGH_BATS,
        COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
        32, 32,
        __setup_cpu_745x
@@ -319,40 +316,18 @@ struct cpu_spec   cpu_specs[] = {
        CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_CAN_NAP |
        CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
        CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR |
-       CPU_FTR_HAS_HIGH_BATS | CPU_FTR_NEED_COHERENT,
-       COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
-       32, 32,
-       __setup_cpu_745x
-    },
-    {  /* 7447/7457 Rev 1.0 */
-       0xffffffff, 0x80020100, "7447/7457",
-       CPU_FTR_COMMON |
-       CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_CAN_NAP |
-       CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
-       CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR |
-       CPU_FTR_HAS_HIGH_BATS | CPU_FTR_NEED_COHERENT | CPU_FTR_NO_BTIC,
-       COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
-       32, 32,
-       __setup_cpu_745x
-    },
-    {  /* 7447/7457 Rev 1.1 */
-       0xffffffff, 0x80020101, "7447/7457",
-       CPU_FTR_COMMON |
-       CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_CAN_NAP |
-       CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
-       CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR |
-       CPU_FTR_HAS_HIGH_BATS | CPU_FTR_NEED_COHERENT | CPU_FTR_NO_BTIC,
+       CPU_FTR_HAS_HIGH_BATS,
        COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
        32, 32,
        __setup_cpu_745x
     },
-    {  /* 7447/7457 Rev 1.2 and later */
-       0xffff0000, 0x80020000, "7447/7457",
+    {  /* 7457 */
+       0xffff0000, 0x80020000, "7457",
        CPU_FTR_COMMON |
        CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_CAN_NAP |
        CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
        CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR |
-       CPU_FTR_HAS_HIGH_BATS | CPU_FTR_NEED_COHERENT,
+       CPU_FTR_HAS_HIGH_BATS,
        COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
        32, 32,
        __setup_cpu_745x
@@ -363,7 +338,7 @@ struct cpu_spec     cpu_specs[] = {
        CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_CAN_NAP |
        CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP |
        CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR |
-       CPU_FTR_HAS_HIGH_BATS | CPU_FTR_NEED_COHERENT,
+       CPU_FTR_HAS_HIGH_BATS,
        COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
        32, 32,
        __setup_cpu_745x
@@ -376,8 +351,8 @@ struct cpu_spec     cpu_specs[] = {
        32, 32,
        __setup_cpu_603
     },
-    {  /* All G2_LE (603e core, plus some) have the same pvr */
-       0x7fff0000, 0x00820000, "G2_LE",
+    {  /* 8280 is a G2_LE (603e core, plus some) */
+       0x7fff0000, 0x00820000, "8280",
        CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_CAN_DOZE | CPU_FTR_USE_TB |
        CPU_FTR_CAN_NAP | CPU_FTR_HAS_HIGH_BATS,
        COMMON_PPC,