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vserver 1.9.3
[linux-2.6.git] / arch / ppc / kernel / cputable.c
diff --git a/arch/ppc/kernel/cputable.c b/arch/ppc/kernel/cputable.c
index b60fa99..605afa6 100644 (file)
--- a/arch/ppc/kernel/cputable.c
+++ b/arch/ppc/kernel/cputable.c
@@ -55,7 +55,7 @@ extern void __setup_cpu_generic(unsigned long offset, int cpu_nr, struct cpu_spe
 #endif
 
 /* We need to mark all pages as being coherent if we're SMP or we
- * have a 754x and an MPC107 host bridge.
+ * have a 74[45]x and an MPC107 host bridge.
  */
 #if defined(CONFIG_SMP) || defined(CONFIG_MPC10X_BRIDGE)
 #define CPU_FTR_COMMON                  CPU_FTR_NEED_COHERENT
@@ -63,6 +63,17 @@ extern void __setup_cpu_generic(unsigned long offset, int cpu_nr, struct cpu_spe
 #define CPU_FTR_COMMON                  0
 #endif
 
+/* The powersave features NAP & DOZE seems to confuse BDI when
+   debugging. So if a BDI is used, disable theses
+ */
+#ifndef CONFIG_BDI_SWITCH
+#define CPU_FTR_MAYBE_CAN_DOZE CPU_FTR_CAN_DOZE
+#define CPU_FTR_MAYBE_CAN_NAP  CPU_FTR_CAN_NAP
+#else
+#define CPU_FTR_MAYBE_CAN_DOZE 0
+#define CPU_FTR_MAYBE_CAN_NAP  0
+#endif
+
 struct cpu_spec        cpu_specs[] = {
 #if CLASSIC_PPC
     {  /* 601 */
@@ -76,8 +87,8 @@ struct cpu_spec       cpu_specs[] = {
     {  /* 603 */
        0xffff0000, 0x00030000, "603",
        CPU_FTR_COMMON |
-       CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_CAN_DOZE | CPU_FTR_USE_TB |
-       CPU_FTR_CAN_NAP,
+       CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB |
+       CPU_FTR_MAYBE_CAN_NAP,
        COMMON_PPC,
        32, 32,
        __setup_cpu_603
@@ -85,8 +96,8 @@ struct cpu_spec       cpu_specs[] = {
     {  /* 603e */
        0xffff0000, 0x00060000, "603e",
        CPU_FTR_COMMON |
-       CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_CAN_DOZE | CPU_FTR_USE_TB |
-       CPU_FTR_CAN_NAP,
+       CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB |
+       CPU_FTR_MAYBE_CAN_NAP,
        COMMON_PPC,
        32, 32,
        __setup_cpu_603
@@ -94,8 +105,8 @@ struct cpu_spec      cpu_specs[] = {
     {  /* 603ev */
        0xffff0000, 0x00070000, "603ev",
        CPU_FTR_COMMON |
-       CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_CAN_DOZE | CPU_FTR_USE_TB |
-       CPU_FTR_CAN_NAP,
+       CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB |
+       CPU_FTR_MAYBE_CAN_NAP,
        COMMON_PPC,
        32, 32,
        __setup_cpu_603
@@ -139,8 +150,8 @@ struct cpu_spec     cpu_specs[] = {
     {  /* 740/750 (0x4202, don't support TAU ?) */
        0xffffffff, 0x00084202, "740/750",
        CPU_FTR_COMMON |
-       CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_CAN_DOZE | CPU_FTR_USE_TB |
-       CPU_FTR_L2CR | CPU_FTR_HPTE_TABLE | CPU_FTR_CAN_NAP,
+       CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB |
+       CPU_FTR_L2CR | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP,
        COMMON_PPC,
        32, 32,
        __setup_cpu_750
@@ -148,8 +159,8 @@ struct cpu_spec     cpu_specs[] = {
     {  /* 745/755 */
        0xfffff000, 0x00083000, "745/755",
        CPU_FTR_COMMON |
-       CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_CAN_DOZE | CPU_FTR_USE_TB |
-       CPU_FTR_L2CR | CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_CAN_NAP,
+       CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB |
+       CPU_FTR_L2CR | CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP,
        COMMON_PPC,
        32, 32,
        __setup_cpu_750
@@ -157,8 +168,8 @@ struct cpu_spec     cpu_specs[] = {
     {  /* 750CX (80100 and 8010x?) */
        0xfffffff0, 0x00080100, "750CX",
        CPU_FTR_COMMON |
-       CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_CAN_DOZE | CPU_FTR_USE_TB |
-       CPU_FTR_L2CR | CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_CAN_NAP,
+       CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB |
+       CPU_FTR_L2CR | CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP,
        COMMON_PPC,
        32, 32,
        __setup_cpu_750cx
@@ -166,8 +177,8 @@ struct cpu_spec     cpu_specs[] = {
     {  /* 750CX (82201 and 82202) */
        0xfffffff0, 0x00082200, "750CX",
        CPU_FTR_COMMON |
-       CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_CAN_DOZE | CPU_FTR_USE_TB |
-       CPU_FTR_L2CR | CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_CAN_NAP,
+       CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB |
+       CPU_FTR_L2CR | CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP,
        COMMON_PPC,
        32, 32,
        __setup_cpu_750cx
@@ -175,8 +186,8 @@ struct cpu_spec     cpu_specs[] = {
     {  /* 750CXe (82214) */
        0xfffffff0, 0x00082210, "750CXe",
        CPU_FTR_COMMON |
-       CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_CAN_DOZE | CPU_FTR_USE_TB |
-       CPU_FTR_L2CR | CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_CAN_NAP,
+       CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB |
+       CPU_FTR_L2CR | CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP,
        COMMON_PPC,
        32, 32,
        __setup_cpu_750cx
@@ -184,8 +195,8 @@ struct cpu_spec     cpu_specs[] = {
     {  /* 750FX rev 1.x */
        0xffffff00, 0x70000100, "750FX",
        CPU_FTR_COMMON |
-       CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_CAN_DOZE | CPU_FTR_USE_TB |
-       CPU_FTR_L2CR | CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_CAN_NAP |
+       CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB |
+       CPU_FTR_L2CR | CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP |
        CPU_FTR_DUAL_PLL_750FX | CPU_FTR_NO_DPM,
        COMMON_PPC,
        32, 32,
@@ -194,8 +205,8 @@ struct cpu_spec     cpu_specs[] = {
     {  /* 750FX rev 2.0 must disable HID0[DPM] */
        0xffffffff, 0x70000200, "750FX",
        CPU_FTR_COMMON |
-       CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_CAN_DOZE | CPU_FTR_USE_TB |
-       CPU_FTR_L2CR | CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_CAN_NAP |
+       CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB |
+       CPU_FTR_L2CR | CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP |
        CPU_FTR_NO_DPM,
        COMMON_PPC,
        32, 32,
@@ -204,8 +215,8 @@ struct cpu_spec     cpu_specs[] = {
     {  /* 750FX (All revs except 2.0) */
        0xffff0000, 0x70000000, "750FX",
        CPU_FTR_COMMON |
-       CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_CAN_DOZE | CPU_FTR_USE_TB |
-       CPU_FTR_L2CR | CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_CAN_NAP |
+       CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB |
+       CPU_FTR_L2CR | CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP |
        CPU_FTR_DUAL_PLL_750FX | CPU_FTR_HAS_HIGH_BATS,
        COMMON_PPC,
        32, 32,
@@ -213,8 +224,8 @@ struct cpu_spec     cpu_specs[] = {
     },
     {  /* 750GX */
        0xffff0000, 0x70020000, "750GX",
-       CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_CAN_DOZE | CPU_FTR_USE_TB |
-       CPU_FTR_L2CR | CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_CAN_NAP |
+       CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB |
+       CPU_FTR_L2CR | CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP |
        CPU_FTR_DUAL_PLL_750FX | CPU_FTR_HAS_HIGH_BATS,
        COMMON_PPC,
        32, 32,
@@ -223,8 +234,8 @@ struct cpu_spec     cpu_specs[] = {
     {  /* 740/750 (L2CR bit need fixup for 740) */
        0xffff0000, 0x00080000, "740/750",
        CPU_FTR_COMMON |
-       CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_CAN_DOZE | CPU_FTR_USE_TB |
-       CPU_FTR_L2CR | CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_CAN_NAP,
+       CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB |
+       CPU_FTR_L2CR | CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP,
        COMMON_PPC,
        32, 32,
        __setup_cpu_750
@@ -232,9 +243,9 @@ struct cpu_spec     cpu_specs[] = {
     {  /* 7400 rev 1.1 ? (no TAU) */
        0xffffffff, 0x000c1101, "7400 (1.1)",
        CPU_FTR_COMMON |
-       CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_CAN_DOZE | CPU_FTR_USE_TB |
+       CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB |
        CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_HPTE_TABLE |
-       CPU_FTR_CAN_NAP,
+       CPU_FTR_MAYBE_CAN_NAP,
        COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
        32, 32,
        __setup_cpu_7400
@@ -242,9 +253,9 @@ struct cpu_spec     cpu_specs[] = {
     {  /* 7400 */
        0xffff0000, 0x000c0000, "7400",
        CPU_FTR_COMMON |
-       CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_CAN_DOZE | CPU_FTR_USE_TB |
+       CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB |
        CPU_FTR_L2CR | CPU_FTR_TAU | CPU_FTR_ALTIVEC_COMP | CPU_FTR_HPTE_TABLE |
-       CPU_FTR_CAN_NAP,
+       CPU_FTR_MAYBE_CAN_NAP,
        COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
        32, 32,
        __setup_cpu_7400
@@ -252,9 +263,9 @@ struct cpu_spec     cpu_specs[] = {
     {  /* 7410 */
        0xffff0000, 0x800c0000, "7410",
        CPU_FTR_COMMON |
-       CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_CAN_DOZE | CPU_FTR_USE_TB |
+       CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB |
        CPU_FTR_L2CR | CPU_FTR_TAU | CPU_FTR_ALTIVEC_COMP | CPU_FTR_HPTE_TABLE |
-       CPU_FTR_CAN_NAP,
+       CPU_FTR_MAYBE_CAN_NAP,
        COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
        32, 32,
        __setup_cpu_7410
@@ -272,7 +283,7 @@ struct cpu_spec     cpu_specs[] = {
     {  /* 7450 2.1 */
        0xffffffff, 0x80000201, "7450",
        CPU_FTR_COMMON |
-       CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_CAN_NAP |
+       CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP |
        CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
        CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR |
        CPU_FTR_L3_DISABLE_NAP | CPU_FTR_NEED_COHERENT,
@@ -283,7 +294,7 @@ struct cpu_spec     cpu_specs[] = {
     {  /* 7450 2.3 and newer */
        0xffff0000, 0x80000000, "7450",
        CPU_FTR_COMMON |
-       CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_CAN_NAP |
+       CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP |
        CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
        CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR |
        CPU_FTR_NEED_COHERENT,
@@ -305,7 +316,7 @@ struct cpu_spec     cpu_specs[] = {
     {  /* 7455 rev 2.0 */
        0xffffffff, 0x80010200, "7455",
        CPU_FTR_COMMON |
-       CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_CAN_NAP |
+       CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP |
        CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
        CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR |
        CPU_FTR_L3_DISABLE_NAP | CPU_FTR_NEED_COHERENT | CPU_FTR_HAS_HIGH_BATS,
@@ -316,7 +327,7 @@ struct cpu_spec     cpu_specs[] = {
     {  /* 7455 others */
        0xffff0000, 0x80010000, "7455",
        CPU_FTR_COMMON |
-       CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_CAN_NAP |
+       CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP |
        CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
        CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR |
        CPU_FTR_HAS_HIGH_BATS | CPU_FTR_NEED_COHERENT,
@@ -327,7 +338,7 @@ struct cpu_spec     cpu_specs[] = {
     {  /* 7447/7457 Rev 1.0 */
        0xffffffff, 0x80020100, "7447/7457",
        CPU_FTR_COMMON |
-       CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_CAN_NAP |
+       CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP |
        CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
        CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR |
        CPU_FTR_HAS_HIGH_BATS | CPU_FTR_NEED_COHERENT | CPU_FTR_NO_BTIC,
@@ -338,7 +349,7 @@ struct cpu_spec     cpu_specs[] = {
     {  /* 7447/7457 Rev 1.1 */
        0xffffffff, 0x80020101, "7447/7457",
        CPU_FTR_COMMON |
-       CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_CAN_NAP |
+       CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP |
        CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
        CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR |
        CPU_FTR_HAS_HIGH_BATS | CPU_FTR_NEED_COHERENT | CPU_FTR_NO_BTIC,
@@ -349,7 +360,7 @@ struct cpu_spec     cpu_specs[] = {
     {  /* 7447/7457 Rev 1.2 and later */
        0xffff0000, 0x80020000, "7447/7457",
        CPU_FTR_COMMON |
-       CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_CAN_NAP |
+       CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP |
        CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
        CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR |
        CPU_FTR_HAS_HIGH_BATS | CPU_FTR_NEED_COHERENT,
@@ -360,7 +371,7 @@ struct cpu_spec     cpu_specs[] = {
     {  /* 7447A */
        0xffff0000, 0x80030000, "7447A",
        CPU_FTR_COMMON |
-       CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_CAN_NAP |
+       CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP |
        CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP |
        CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR |
        CPU_FTR_HAS_HIGH_BATS | CPU_FTR_NEED_COHERENT,
@@ -371,15 +382,15 @@ struct cpu_spec   cpu_specs[] = {
     {  /* 82xx (8240, 8245, 8260 are all 603e cores) */
        0x7fff0000, 0x00810000, "82xx",
        CPU_FTR_COMMON |
-       CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_CAN_DOZE | CPU_FTR_USE_TB,
+       CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB,
        COMMON_PPC,
        32, 32,
        __setup_cpu_603
     },
     {  /* All G2_LE (603e core, plus some) have the same pvr */
        0x7fff0000, 0x00820000, "G2_LE",
-       CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_CAN_DOZE | CPU_FTR_USE_TB |
-       CPU_FTR_CAN_NAP | CPU_FTR_HAS_HIGH_BATS,
+       CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB |
+       CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_HAS_HIGH_BATS,
        COMMON_PPC,
        32, 32,
        __setup_cpu_603
@@ -440,7 +451,16 @@ struct cpu_spec    cpu_specs[] = {
        0xffff0000, 0x00390000, "PPC970",
        CPU_FTR_COMMON |
        CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE |
-       CPU_FTR_ALTIVEC_COMP | CPU_FTR_CAN_NAP,
+       CPU_FTR_ALTIVEC_COMP | CPU_FTR_MAYBE_CAN_NAP,
+       COMMON_PPC | PPC_FEATURE_64 | PPC_FEATURE_ALTIVEC_COMP,
+       128, 128,
+       __setup_cpu_ppc970
+    },
+    {  /* PPC970FX */
+       0xffff0000, 0x003c0000, "PPC970FX",
+       CPU_FTR_COMMON |
+       CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE |
+       CPU_FTR_ALTIVEC_COMP | CPU_FTR_MAYBE_CAN_NAP,
        COMMON_PPC | PPC_FEATURE_64 | PPC_FEATURE_ALTIVEC_COMP,
        128, 128,
        __setup_cpu_ppc970
@@ -449,7 +469,8 @@ struct cpu_spec     cpu_specs[] = {
 #ifdef CONFIG_8xx
     {  /* 8xx */
        0xffff0000, 0x00500000, "8xx",
-               /* CPU_FTR_CAN_DOZE is possible, if the 8xx code is there.... */
+               /* CPU_FTR_MAYBE_CAN_DOZE is possible,
+                * if the 8xx code is there.... */
        CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB,
        PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
        16, 16,
@@ -590,7 +611,7 @@ struct cpu_spec     cpu_specs[] = {
 #ifdef CONFIG_E500
     { /* e500 */
         0xffff0000, 0x80200000, "e500",
-       /* xxx - galak: add CPU_FTR_CAN_DOZE */
+       /* xxx - galak: add CPU_FTR_MAYBE_CAN_DOZE */
         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB,
         PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
         32, 32,
linux-2.6