32, 32,
__setup_cpu_750fx
},
-
+ { /* 750GX */
+ 0xffff0000, 0x70020000, "750GX",
+ CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_CAN_DOZE | CPU_FTR_USE_TB |
+ CPU_FTR_L2CR | CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_CAN_NAP |
+ CPU_FTR_DUAL_PLL_750FX | CPU_FTR_HAS_HIGH_BATS,
+ COMMON_PPC,
+ 32, 32,
+ __setup_cpu_750fx
+ },
{ /* 740/750 (L2CR bit need fixup for 740) */
0xffff0000, 0x00080000, "740/750",
CPU_FTR_COMMON |
32, 32,
__setup_cpu_603
},
+ { /* 8280 is a G2_LE (603e core, plus some) */
+ 0x7fff0000, 0x00820000, "8280",
+ CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_CAN_DOZE | CPU_FTR_USE_TB |
+ CPU_FTR_CAN_NAP | CPU_FTR_HAS_HIGH_BATS,
+ COMMON_PPC,
+ 32, 32,
+ __setup_cpu_603
+ },
{ /* default match, we assume split I/D cache & TB (non-601)... */
0x00000000, 0x00000000, "(generic PPC)",
CPU_FTR_COMMON |
32, 32,
0, /*__setup_cpu_440 */
},
- { /* 440GX Rev. B1 (2.1) */
- 0xf0000fff, 0x50000852, "440GX Rev. B1 (2.1)",
+ { /* 440GX Rev. C */
+ 0xf0000fff, 0x50000892, "440GX Rev. C",
CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB,
PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
32, 32,