#include <asm/ppc_asm.h>
#include <asm/offsets.h>
+/* Macro to make the code more readable. */
+#ifdef CONFIG_8xx_CPU6
+#define DO_8xx_CPU6(val, reg) \
+ li reg, val; \
+ stw reg, 12(r0); \
+ lwz reg, 12(r0);
+#else
+#define DO_8xx_CPU6(val, reg)
+#endif
.text
.globl _stext
_stext:
-
-/*
- * _start is defined this way because the XCOFF loader in the OpenFirmware
- * on the powermac expects the entry point to be a procedure descriptor.
- */
.text
.globl _start
_start:
* and the CCR at memory location 0.....Someday I'll fix this.....
* -- Dan
*/
-
.globl __start
__start:
mr r31,r3 /* save parameters */
mr r29,r5
mr r28,r6
mr r27,r7
- li r24,0 /* cpu # */
/* We have to turn on the MMU right away so we get cache modes
* set correctly.
* task's thread_struct.
*/
#define EXCEPTION_PROLOG \
- mtspr SPRG0,r20; \
- mtspr SPRG1,r21; \
- mfcr r20; \
- mfspr r21,SPRG2; /* exception stack to use from */ \
- cmpwi 0,r21,0; /* user mode or RTAS */ \
- bne 1f; \
- tophys(r21,r1); /* use tophys(kernel sp) otherwise */ \
- subi r21,r21,INT_FRAME_SIZE; /* alloc exc. frame */\
-1: stw r20,_CCR(r21); /* save registers */ \
- stw r22,GPR22(r21); \
- stw r23,GPR23(r21); \
- mfspr r20,SPRG0; \
- stw r20,GPR20(r21); \
- mfspr r22,SPRG1; \
- stw r22,GPR21(r21); \
- mflr r20; \
- stw r20,_LINK(r21); \
- mfctr r22; \
- stw r22,_CTR(r21); \
- mfspr r20,XER; \
- stw r20,_XER(r21); \
- mfspr r22,SRR0; \
- mfspr r23,SRR1; \
- stw r0,GPR0(r21); \
- stw r1,GPR1(r21); \
- stw r2,GPR2(r21); \
- stw r1,0(r21); \
- tovirt(r1,r21); /* set new kernel sp */ \
- SAVE_4GPRS(3, r21); \
- SAVE_GPR(7, r21);
+ mtspr SPRG0,r10; \
+ mtspr SPRG1,r11; \
+ mfcr r10; \
+ EXCEPTION_PROLOG_1; \
+ EXCEPTION_PROLOG_2
+
+#define EXCEPTION_PROLOG_1 \
+ mfspr r11,SRR1; /* check whether user or kernel */ \
+ andi. r11,r11,MSR_PR; \
+ tophys(r11,r1); /* use tophys(r1) if kernel */ \
+ beq 1f; \
+ mfspr r11,SPRG3; \
+ lwz r11,THREAD_INFO-THREAD(r11); \
+ addi r11,r11,THREAD_SIZE; \
+ tophys(r11,r11); \
+1: subi r11,r11,INT_FRAME_SIZE /* alloc exc. frame */
+
+
+#define EXCEPTION_PROLOG_2 \
+ CLR_TOP32(r11); \
+ stw r10,_CCR(r11); /* save registers */ \
+ stw r12,GPR12(r11); \
+ stw r9,GPR9(r11); \
+ mfspr r10,SPRG0; \
+ stw r10,GPR10(r11); \
+ mfspr r12,SPRG1; \
+ stw r12,GPR11(r11); \
+ mflr r10; \
+ stw r10,_LINK(r11); \
+ mfspr r12,SRR0; \
+ mfspr r9,SRR1; \
+ stw r1,GPR1(r11); \
+ stw r1,0(r11); \
+ tovirt(r1,r11); /* set new kernel sp */ \
+ li r10,MSR_KERNEL & ~(MSR_IR|MSR_DR); /* can take exceptions */ \
+ MTMSRD(r10); /* (except for mach check in rtas) */ \
+ stw r0,GPR0(r11); \
+ SAVE_4GPRS(3, r11); \
+ SAVE_2GPRS(7, r11)
+
/*
* Note: code which follows this uses cr0.eq (set if from kernel),
- * r21, r22 (SRR0), and r23 (SRR1).
+ * r11, r12 (SRR0), and r9 (SRR1).
+ *
+ * Note2: once we have set r1 we are in a position to take exceptions
+ * again, and we could thus set MSR:RI at that point.
*/
/*
* Exception vectors.
*/
-#define STD_EXCEPTION(n, label, hdlr) \
+#define EXCEPTION(n, label, hdlr, xfer) \
. = n; \
label: \
EXCEPTION_PROLOG; \
addi r3,r1,STACK_FRAME_OVERHEAD; \
- li r20,MSR_KERNEL; \
- bl transfer_to_handler; \
- .long hdlr; \
- .long ret_from_except
+ xfer(n, hdlr)
+
+#define EXC_XFER_TEMPLATE(n, hdlr, trap, copyee, tfer, ret) \
+ li r10,trap; \
+ stw r10,TRAP(r11); \
+ li r10,MSR_KERNEL; \
+ copyee(r10, r9); \
+ bl tfer; \
+i##n: \
+ .long hdlr; \
+ .long ret
+
+#define COPY_EE(d, s) rlwimi d,s,0,16,16
+#define NOCOPY(d, s)
+
+#define EXC_XFER_STD(n, hdlr) \
+ EXC_XFER_TEMPLATE(n, hdlr, n, NOCOPY, transfer_to_handler_full, \
+ ret_from_except_full)
+
+#define EXC_XFER_LITE(n, hdlr) \
+ EXC_XFER_TEMPLATE(n, hdlr, n+1, NOCOPY, transfer_to_handler, \
+ ret_from_except)
+
+#define EXC_XFER_EE(n, hdlr) \
+ EXC_XFER_TEMPLATE(n, hdlr, n, COPY_EE, transfer_to_handler_full, \
+ ret_from_except_full)
+
+#define EXC_XFER_EE_LITE(n, hdlr) \
+ EXC_XFER_TEMPLATE(n, hdlr, n+1, COPY_EE, transfer_to_handler, \
+ ret_from_except)
/* System reset */
-#ifdef CONFIG_SMP /* MVME/MTX start the secondary here */
- STD_EXCEPTION(0x100, Reset, __secondary_start_psurge)
-#else
- STD_EXCEPTION(0x100, Reset, UnknownException)
-#endif
+ EXCEPTION(0x100, Reset, UnknownException, EXC_XFER_STD)
/* Machine check */
- STD_EXCEPTION(0x200, MachineCheck, MachineCheckException)
+ . = 0x200
+MachineCheck:
+ EXCEPTION_PROLOG
+ mfspr r4,DAR
+ stw r4,_DAR(r11)
+ mfspr r5,DSISR
+ stw r5,_DSISR(r11)
+ addi r3,r1,STACK_FRAME_OVERHEAD
+ EXC_XFER_STD(0x200, MachineCheckException)
/* Data access exception.
* This is "never generated" by the MPC8xx. We jump to it for other
. = 0x300
DataAccess:
EXCEPTION_PROLOG
- mfspr r20,DSISR
- stw r20,_DSISR(r21)
- mr r5,r20
+ mfspr r10,DSISR
+ stw r10,_DSISR(r11)
+ mr r5,r10
mfspr r4,DAR
- stw r4,_DAR(r21)
- addi r3,r1,STACK_FRAME_OVERHEAD
- li r20,MSR_KERNEL
- rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */
- bl transfer_to_handler
- .long do_page_fault
- .long ret_from_except
+ EXC_XFER_EE_LITE(0x300, handle_page_fault)
/* Instruction access exception.
* This is "never generated" by the MPC8xx. We jump to it for other
. = 0x400
InstructionAccess:
EXCEPTION_PROLOG
- addi r3,r1,STACK_FRAME_OVERHEAD
- mr r4,r22
- mr r5,r23
- li r20,MSR_KERNEL
- rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */
- bl transfer_to_handler
- .long do_page_fault
- .long ret_from_except
+ mr r4,r12
+ mr r5,r9
+ EXC_XFER_EE_LITE(0x400, handle_page_fault)
/* External interrupt */
- . = 0x500;
-HardwareInterrupt:
- EXCEPTION_PROLOG;
- addi r3,r1,STACK_FRAME_OVERHEAD
- li r20,MSR_KERNEL
- li r4,0
- bl transfer_to_handler
- .globl do_IRQ_intercept
-do_IRQ_intercept:
- .long do_IRQ;
- .long ret_from_intercept
-
+ EXCEPTION(0x500, HardwareInterrupt, do_IRQ, EXC_XFER_LITE)
/* Alignment exception */
. = 0x600
Alignment:
EXCEPTION_PROLOG
mfspr r4,DAR
- stw r4,_DAR(r21)
+ stw r4,_DAR(r11)
mfspr r5,DSISR
- stw r5,_DSISR(r21)
+ stw r5,_DSISR(r11)
addi r3,r1,STACK_FRAME_OVERHEAD
- li r20,MSR_KERNEL
- rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */
- bl transfer_to_handler
- .long AlignmentException
- .long ret_from_except
+ EXC_XFER_EE(0x600, AlignmentException)
/* Program check exception */
- . = 0x700
-ProgramCheck:
- EXCEPTION_PROLOG
- addi r3,r1,STACK_FRAME_OVERHEAD
- li r20,MSR_KERNEL
- rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */
- bl transfer_to_handler
- .long ProgramCheckException
- .long ret_from_except
+ EXCEPTION(0x700, ProgramCheck, ProgramCheckException, EXC_XFER_STD)
/* No FPU on MPC8xx. This exception is not supposed to happen.
*/
- STD_EXCEPTION(0x800, FPUnavailable, UnknownException)
+ EXCEPTION(0x800, FPUnavailable, UnknownException, EXC_XFER_STD)
- . = 0x900
-Decrementer:
- EXCEPTION_PROLOG
- addi r3,r1,STACK_FRAME_OVERHEAD
- li r20,MSR_KERNEL
- bl transfer_to_handler
- .globl timer_interrupt_intercept
-timer_interrupt_intercept:
- .long timer_interrupt
- .long ret_from_intercept
+/* Decrementer */
+ EXCEPTION(0x900, Decrementer, timer_interrupt, EXC_XFER_LITE)
- STD_EXCEPTION(0xa00, Trap_0a, UnknownException)
- STD_EXCEPTION(0xb00, Trap_0b, UnknownException)
+ EXCEPTION(0xa00, Trap_0a, UnknownException, EXC_XFER_EE)
+ EXCEPTION(0xb00, Trap_0b, UnknownException, EXC_XFER_EE)
/* System call */
. = 0xc00
SystemCall:
EXCEPTION_PROLOG
- stw r3,ORIG_GPR3(r21)
- li r20,MSR_KERNEL
- rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */
- bl transfer_to_handler
- .long DoSyscall
- .long ret_from_except
+ EXC_XFER_EE_LITE(0xc00, DoSyscall)
/* Single step - not used on 601 */
- STD_EXCEPTION(0xd00, SingleStep, SingleStepException)
-
- STD_EXCEPTION(0xe00, Trap_0e, UnknownException)
- STD_EXCEPTION(0xf00, Trap_0f, UnknownException)
+ EXCEPTION(0xd00, SingleStep, SingleStepException, EXC_XFER_STD)
+ EXCEPTION(0xe00, Trap_0e, UnknownException, EXC_XFER_EE)
+ EXCEPTION(0xf00, Trap_0f, UnknownException, EXC_XFER_EE)
/* On the MPC8xx, this is a software emulation interrupt. It occurs
* for all unimplemented and illegal instructions.
*/
- STD_EXCEPTION(0x1000, SoftEmu, SoftwareEmulation)
+ EXCEPTION(0x1000, SoftEmu, SoftwareEmulation, EXC_XFER_STD)
. = 0x1100
/*
InstructionTLBMiss:
#ifdef CONFIG_8xx_CPU6
stw r3, 8(r0)
- li r3, 0x3f80
- stw r3, 12(r0)
- lwz r3, 12(r0)
-#endif
- mtspr M_TW, r20 /* Save a couple of working registers */
- mfcr r20
- stw r20, 0(r0)
- stw r21, 4(r0)
- mfspr r20, SRR0 /* Get effective address of fault */
-#ifdef CONFIG_8xx_CPU6
- li r3, 0x3780
- stw r3, 12(r0)
- lwz r3, 12(r0)
#endif
- mtspr MD_EPN, r20 /* Have to use MD_EPN for walk, MI_EPN can't */
- mfspr r20, M_TWB /* Get level 1 table entry address */
+ DO_8xx_CPU6(0x3f80, r3)
+ mtspr M_TW, r10 /* Save a couple of working registers */
+ mfcr r10
+ stw r10, 0(r0)
+ stw r11, 4(r0)
+ mfspr r10, SRR0 /* Get effective address of fault */
+ DO_8xx_CPU6(0x3780, r3)
+ mtspr MD_EPN, r10 /* Have to use MD_EPN for walk, MI_EPN can't */
+ mfspr r10, M_TWB /* Get level 1 table entry address */
/* If we are faulting a kernel address, we have to use the
* kernel page tables.
*/
- andi. r21, r20, 0x0800 /* Address >= 0x80000000 */
+ andi. r11, r10, 0x0800 /* Address >= 0x80000000 */
beq 3f
- lis r21, swapper_pg_dir@h
- ori r21, r21, swapper_pg_dir@l
- rlwimi r20, r21, 0, 2, 19
+ lis r11, swapper_pg_dir@h
+ ori r11, r11, swapper_pg_dir@l
+ rlwimi r10, r11, 0, 2, 19
3:
- lwz r21, 0(r20) /* Get the level 1 entry */
- rlwinm. r20, r21,0,0,19 /* Extract page descriptor page address */
+ lwz r11, 0(r10) /* Get the level 1 entry */
+ rlwinm. r10, r11,0,0,19 /* Extract page descriptor page address */
beq 2f /* If zero, don't try to find a pte */
/* We have a pte table, so load the MI_TWC with the attributes
* for this "segment."
*/
- tophys(r21,r21)
- ori r21,r21,1 /* Set valid bit */
-#ifdef CONFIG_8xx_CPU6
- li r3, 0x2b80
- stw r3, 12(r0)
- lwz r3, 12(r0)
-#endif
- mtspr MI_TWC, r21 /* Set segment attributes */
-#ifdef CONFIG_8xx_CPU6
- li r3, 0x3b80
- stw r3, 12(r0)
- lwz r3, 12(r0)
-#endif
- mtspr MD_TWC, r21 /* Load pte table base address */
- mfspr r21, MD_TWC /* ....and get the pte address */
- lwz r20, 0(r21) /* Get the pte */
+ ori r11,r11,1 /* Set valid bit */
+ DO_8xx_CPU6(0x2b80, r3)
+ mtspr MI_TWC, r11 /* Set segment attributes */
+ DO_8xx_CPU6(0x3b80, r3)
+ mtspr MD_TWC, r11 /* Load pte table base address */
+ mfspr r11, MD_TWC /* ....and get the pte address */
+ lwz r10, 0(r11) /* Get the pte */
- ori r20, r20, _PAGE_ACCESSED
- stw r20, 0(r21)
+ ori r10, r10, _PAGE_ACCESSED
+ stw r10, 0(r11)
/* The Linux PTE won't go exactly into the MMU TLB.
* Software indicator bits 21, 22 and 28 must be clear.
* set. All other Linux PTE bits control the behavior
* of the MMU.
*/
- li r21, 0x00f0
- rlwimi r20, r21, 0, 24, 28 /* Set 24-27, clear 28 */
-
-#ifdef CONFIG_8xx_CPU6
- li r3, 0x2d80
- stw r3, 12(r0)
- lwz r3, 12(r0)
-#endif
- mtspr MI_RPN, r20 /* Update TLB entry */
-
- mfspr r20, M_TW /* Restore registers */
- lwz r21, 0(r0)
- mtcr r21
- lwz r21, 4(r0)
+2: li r11, 0x00f0
+ rlwimi r10, r11, 0, 24, 28 /* Set 24-27, clear 28 */
+ DO_8xx_CPU6(0x2d80, r3)
+ mtspr MI_RPN, r10 /* Update TLB entry */
+
+ mfspr r10, M_TW /* Restore registers */
+ lwz r11, 0(r0)
+ mtcr r11
+ lwz r11, 4(r0)
#ifdef CONFIG_8xx_CPU6
lwz r3, 8(r0)
#endif
rfi
-2: mfspr r20, M_TW /* Restore registers */
- lwz r21, 0(r0)
- mtcr r21
- lwz r21, 4(r0)
-#ifdef CONFIG_8xx_CPU6
- lwz r3, 8(r0)
-#endif
- b InstructionAccess
-
. = 0x1200
DataStoreTLBMiss:
#ifdef CONFIG_8xx_CPU6
stw r3, 8(r0)
- li r3, 0x3f80
- stw r3, 12(r0)
- lwz r3, 12(r0)
#endif
- mtspr M_TW, r20 /* Save a couple of working registers */
- mfcr r20
- stw r20, 0(r0)
- stw r21, 4(r0)
- mfspr r20, M_TWB /* Get level 1 table entry address */
+ DO_8xx_CPU6(0x3f80, r3)
+ mtspr M_TW, r10 /* Save a couple of working registers */
+ mfcr r10
+ stw r10, 0(r0)
+ stw r11, 4(r0)
+ mfspr r10, M_TWB /* Get level 1 table entry address */
/* If we are faulting a kernel address, we have to use the
* kernel page tables.
*/
- andi. r21, r20, 0x0800
+ andi. r11, r10, 0x0800
beq 3f
- lis r21, swapper_pg_dir@h
- ori r21, r21, swapper_pg_dir@l
- rlwimi r20, r21, 0, 2, 19
+ lis r11, swapper_pg_dir@h
+ ori r11, r11, swapper_pg_dir@l
+ rlwimi r10, r11, 0, 2, 19
3:
- lwz r21, 0(r20) /* Get the level 1 entry */
- rlwinm. r20, r21,0,0,19 /* Extract page descriptor page address */
+ lwz r11, 0(r10) /* Get the level 1 entry */
+ rlwinm. r10, r11,0,0,19 /* Extract page descriptor page address */
beq 2f /* If zero, don't try to find a pte */
/* We have a pte table, so load fetch the pte from the table.
*/
- tophys(r21, r21)
- ori r21, r21, 1 /* Set valid bit in physical L2 page */
-#ifdef CONFIG_8xx_CPU6
- li r3, 0x3b80
- stw r3, 12(r0)
- lwz r3, 12(r0)
-#endif
- mtspr MD_TWC, r21 /* Load pte table base address */
- mfspr r20, MD_TWC /* ....and get the pte address */
- lwz r20, 0(r20) /* Get the pte */
+ ori r11, r11, 1 /* Set valid bit in physical L2 page */
+ DO_8xx_CPU6(0x3b80, r3)
+ mtspr MD_TWC, r11 /* Load pte table base address */
+ mfspr r10, MD_TWC /* ....and get the pte address */
+ lwz r10, 0(r10) /* Get the pte */
/* Insert the Guarded flag into the TWC from the Linux PTE.
* It is bit 27 of both the Linux PTE and the TWC (at least
* this into the Linux pgd/pmd and load it in the operation
* above.
*/
- rlwimi r21, r20, 0, 27, 27
-#ifdef CONFIG_8xx_CPU6
- li r3, 0x3b80
- stw r3, 12(r0)
- lwz r3, 12(r0)
-#endif
- mtspr MD_TWC, r21
+ rlwimi r11, r10, 0, 27, 27
+ DO_8xx_CPU6(0x3b80, r3)
+ mtspr MD_TWC, r11
- mfspr r21, MD_TWC /* get the pte address again */
- ori r20, r20, _PAGE_ACCESSED
- stw r20, 0(r21)
+ mfspr r11, MD_TWC /* get the pte address again */
+ ori r10, r10, _PAGE_ACCESSED
+ stw r10, 0(r11)
/* The Linux PTE won't go exactly into the MMU TLB.
* Software indicator bits 21, 22 and 28 must be clear.
* set. All other Linux PTE bits control the behavior
* of the MMU.
*/
- li r21, 0x00f0
- rlwimi r20, r21, 0, 24, 28 /* Set 24-27, clear 28 */
-
-#ifdef CONFIG_8xx_CPU6
- li r3, 0x3d80
- stw r3, 12(r0)
- lwz r3, 12(r0)
-#endif
- mtspr MD_RPN, r20 /* Update TLB entry */
-
- mfspr r20, M_TW /* Restore registers */
- lwz r21, 0(r0)
- mtcr r21
- lwz r21, 4(r0)
+2: li r11, 0x00f0
+ rlwimi r10, r11, 0, 24, 28 /* Set 24-27, clear 28 */
+ DO_8xx_CPU6(0x3d80, r3)
+ mtspr MD_RPN, r10 /* Update TLB entry */
+
+ mfspr r10, M_TW /* Restore registers */
+ lwz r11, 0(r0)
+ mtcr r11
+ lwz r11, 4(r0)
#ifdef CONFIG_8xx_CPU6
lwz r3, 8(r0)
#endif
rfi
-2: mfspr r20, M_TW /* Restore registers */
- lwz r21, 0(r0)
- mtcr r21
- lwz r21, 4(r0)
-#ifdef CONFIG_8xx_CPU6
- lwz r3, 8(r0)
-#endif
- b DataAccess
-
/* This is an instruction TLB error on the MPC8xx. This could be due
* to many reasons, such as executing guarded memory or illegal instruction
* addresses. There is nothing to do but handle a big time error fault.
DataTLBError:
#ifdef CONFIG_8xx_CPU6
stw r3, 8(r0)
- li r3, 0x3f80
- stw r3, 12(r0)
- lwz r3, 12(r0)
#endif
- mtspr M_TW, r20 /* Save a couple of working registers */
- mfcr r20
- stw r20, 0(r0)
- stw r21, 4(r0)
+ DO_8xx_CPU6(0x3f80, r3)
+ mtspr M_TW, r10 /* Save a couple of working registers */
+ mfcr r10
+ stw r10, 0(r0)
+ stw r11, 4(r0)
/* First, make sure this was a store operation.
*/
- mfspr r20, DSISR
- andis. r21, r20, 0x0200 /* If set, indicates store op */
+ mfspr r10, DSISR
+ andis. r11, r10, 0x0200 /* If set, indicates store op */
beq 2f
/* The EA of a data TLB miss is automatically stored in the MD_EPN
* are initialized in mapin_ram(). This will avoid the problem,
* assuming we only use the dcbi instruction on kernel addresses.
*/
- mfspr r20, DAR
- rlwinm r21, r20, 0, 0, 19
- ori r21, r21, MD_EVALID
- mfspr r20, M_CASID
- rlwimi r21, r20, 0, 28, 31
-#ifdef CONFIG_8xx_CPU6
- li r3, 0x3780
- stw r3, 12(r0)
- lwz r3, 12(r0)
-#endif
- mtspr MD_EPN, r21
+ mfspr r10, DAR
+ rlwinm r11, r10, 0, 0, 19
+ ori r11, r11, MD_EVALID
+ mfspr r10, M_CASID
+ rlwimi r11, r10, 0, 28, 31
+ DO_8xx_CPU6(0x3780, r3)
+ mtspr MD_EPN, r11
- mfspr r20, M_TWB /* Get level 1 table entry address */
+ mfspr r10, M_TWB /* Get level 1 table entry address */
/* If we are faulting a kernel address, we have to use the
* kernel page tables.
*/
- andi. r21, r20, 0x0800
+ andi. r11, r10, 0x0800
beq 3f
- lis r21, swapper_pg_dir@h
- ori r21, r21, swapper_pg_dir@l
- rlwimi r20, r21, 0, 2, 19
+ lis r11, swapper_pg_dir@h
+ ori r11, r11, swapper_pg_dir@l
+ rlwimi r10, r11, 0, 2, 19
3:
- lwz r21, 0(r20) /* Get the level 1 entry */
- rlwinm. r20, r21,0,0,19 /* Extract page descriptor page address */
+ lwz r11, 0(r10) /* Get the level 1 entry */
+ rlwinm. r10, r11,0,0,19 /* Extract page descriptor page address */
beq 2f /* If zero, bail */
/* We have a pte table, so fetch the pte from the table.
*/
- tophys(r21, r21)
- ori r21, r21, 1 /* Set valid bit in physical L2 page */
-#ifdef CONFIG_8xx_CPU6
- li r3, 0x3b80
- stw r3, 12(r0)
- lwz r3, 12(r0)
-#endif
- mtspr MD_TWC, r21 /* Load pte table base address */
- mfspr r21, MD_TWC /* ....and get the pte address */
- lwz r20, 0(r21) /* Get the pte */
+ ori r11, r11, 1 /* Set valid bit in physical L2 page */
+ DO_8xx_CPU6(0x3b80, r3)
+ mtspr MD_TWC, r11 /* Load pte table base address */
+ mfspr r11, MD_TWC /* ....and get the pte address */
+ lwz r10, 0(r11) /* Get the pte */
- andi. r21, r20, _PAGE_RW /* Is it writeable? */
+ andi. r11, r10, _PAGE_RW /* Is it writeable? */
beq 2f /* Bail out if not */
/* Update 'changed', among others.
*/
- ori r20, r20, _PAGE_DIRTY|_PAGE_ACCESSED|_PAGE_HWWRITE
- mfspr r21, MD_TWC /* Get pte address again */
- stw r20, 0(r21) /* and update pte in table */
+ ori r10, r10, _PAGE_DIRTY|_PAGE_ACCESSED|_PAGE_HWWRITE
+ mfspr r11, MD_TWC /* Get pte address again */
+ stw r10, 0(r11) /* and update pte in table */
/* The Linux PTE won't go exactly into the MMU TLB.
* Software indicator bits 21, 22 and 28 must be clear.
* set. All other Linux PTE bits control the behavior
* of the MMU.
*/
- li r21, 0x00f0
- rlwimi r20, r21, 0, 24, 28 /* Set 24-27, clear 28 */
-
-#ifdef CONFIG_8xx_CPU6
- li r3, 0x3d80
- stw r3, 12(r0)
- lwz r3, 12(r0)
-#endif
- mtspr MD_RPN, r20 /* Update TLB entry */
-
- mfspr r20, M_TW /* Restore registers */
- lwz r21, 0(r0)
- mtcr r21
- lwz r21, 4(r0)
+ li r11, 0x00f0
+ rlwimi r10, r11, 0, 24, 28 /* Set 24-27, clear 28 */
+ DO_8xx_CPU6(0x3d80, r3)
+ mtspr MD_RPN, r10 /* Update TLB entry */
+
+ mfspr r10, M_TW /* Restore registers */
+ lwz r11, 0(r0)
+ mtcr r11
+ lwz r11, 4(r0)
#ifdef CONFIG_8xx_CPU6
lwz r3, 8(r0)
#endif
rfi
2:
- mfspr r20, M_TW /* Restore registers */
- lwz r21, 0(r0)
- mtcr r21
- lwz r21, 4(r0)
+ mfspr r10, M_TW /* Restore registers */
+ lwz r11, 0(r0)
+ mtcr r11
+ lwz r11, 4(r0)
#ifdef CONFIG_8xx_CPU6
lwz r3, 8(r0)
#endif
b DataAccess
- STD_EXCEPTION(0x1500, Trap_15, UnknownException)
- STD_EXCEPTION(0x1600, Trap_16, UnknownException)
- STD_EXCEPTION(0x1700, Trap_17, TAUException)
- STD_EXCEPTION(0x1800, Trap_18, UnknownException)
- STD_EXCEPTION(0x1900, Trap_19, UnknownException)
- STD_EXCEPTION(0x1a00, Trap_1a, UnknownException)
- STD_EXCEPTION(0x1b00, Trap_1b, UnknownException)
+ EXCEPTION(0x1500, Trap_15, UnknownException, EXC_XFER_EE)
+ EXCEPTION(0x1600, Trap_16, UnknownException, EXC_XFER_EE)
+ EXCEPTION(0x1700, Trap_17, UnknownException, EXC_XFER_EE)
+ EXCEPTION(0x1800, Trap_18, UnknownException, EXC_XFER_EE)
+ EXCEPTION(0x1900, Trap_19, UnknownException, EXC_XFER_EE)
+ EXCEPTION(0x1a00, Trap_1a, UnknownException, EXC_XFER_EE)
+ EXCEPTION(0x1b00, Trap_1b, UnknownException, EXC_XFER_EE)
/* On the MPC8xx, these next four traps are used for development
* support of breakpoints and such. Someday I will get around to
* using them.
*/
- STD_EXCEPTION(0x1c00, Trap_1c, UnknownException)
- STD_EXCEPTION(0x1d00, Trap_1d, UnknownException)
- STD_EXCEPTION(0x1e00, Trap_1e, UnknownException)
- STD_EXCEPTION(0x1f00, Trap_1f, UnknownException)
+ EXCEPTION(0x1c00, Trap_1c, UnknownException, EXC_XFER_EE)
+ EXCEPTION(0x1d00, Trap_1d, UnknownException, EXC_XFER_EE)
+ EXCEPTION(0x1e00, Trap_1e, UnknownException, EXC_XFER_EE)
+ EXCEPTION(0x1f00, Trap_1f, UnknownException, EXC_XFER_EE)
. = 0x2000
giveup_fpu:
blr
-/* Maybe someday.......
-*/
-_GLOBAL(__setup_cpu_8xx)
- blr
-
/*
* This is where the main kernel code starts.
*/
git://git.onelab.eu / linux-2.6.git / blobdiff