vserver 1.9.5.x5

[linux-2.6.git] / arch / ppc / kernel / l2cr.S

diff --git a/arch/ppc/kernel/l2cr.S b/arch/ppc/kernel/l2cr.S
index b362b15..8abf2ee 100644 (file)
--- a/arch/ppc/kernel/l2cr.S
+++ b/arch/ppc/kernel/l2cr.S
@@ -45,6 +45,7 @@
 #include <asm/cputable.h>
 #include <asm/ppc_asm.h>
 #include <asm/cache.h>
+#include <asm/page.h>
 
 /* Usage:
 
@@ -284,7 +285,7 @@ END_FTR_SECTION_IFCLR(CPU_FTR_L3CR)
        /* Tweak some bits */
        rlwinm  r5,r3,0,0,0             /* r5 contains the new enable bit */
        rlwinm  r3,r3,0,22,20           /* Turn off the invalidate bit */
-       rlwinm  r3,r3,0,1,31            /* Turn off the enable bit */
+       rlwinm  r3,r3,0,2,31            /* Turn off the enable & PE bits */
        rlwinm  r3,r3,0,5,3             /* Turn off the clken bit */
        /* Check to see if we need to flush */
        rlwinm. r4,r4,0,0,0
@@ -379,7 +380,7 @@ END_FTR_SECTION_IFSET(CPU_FTR_L3CR)
 /* flush_disable_L1()  - Flush and disable L1 cache
  *
  * clobbers r0, r3, ctr, cr0
- *
+ * Must be called with interrupts disabled and MMU enabled.
  */
 _GLOBAL(__flush_disable_L1)
        /* Stop pending alitvec streams and memory accesses */
@@ -393,7 +394,7 @@ END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
         */
        li      r3,0x4000       /* 512kB / 32B */
        mtctr   r3
-       li      r3, 0
+       lis     r3,KERNELBASE@h
 1:
        lwz     r0,0(r3)
        addi    r3,r3,0x0020    /* Go to start of next cache line */
@@ -404,7 +405,7 @@ END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
        /* Now flush those cache lines */
        li      r3,0x4000       /* 512kB / 32B */
        mtctr   r3
-       li      r3, 0
+       lis     r3,KERNELBASE@h
 1:
        dcbf    0,r3
        addi    r3,r3,0x0020    /* Go to start of next cache line */