patch-2_6_7-vs1_9_1_12

[linux-2.6.git] / arch / ppc / kernel / traps.c

diff --git a/arch/ppc/kernel/traps.c b/arch/ppc/kernel/traps.c
index 197b862..cc50022 100644 (file)
--- a/arch/ppc/kernel/traps.c
+++ b/arch/ppc/kernel/traps.c
@@ -41,9 +41,6 @@
 #include <asm/backlight.h>
 #endif
 
-extern int fix_alignment(struct pt_regs *);
-extern void bad_page_fault(struct pt_regs *, unsigned long, int sig);
-
 #ifdef CONFIG_XMON
 void (*debugger)(struct pt_regs *regs) = xmon;
 int (*debugger_bpt)(struct pt_regs *regs) = xmon_bpt;
@@ -222,14 +219,43 @@ MachineCheckException(struct pt_regs *regs)
        if (check_io_access(regs))
                return;
 
-#ifdef CONFIG_4xx
+#if defined(CONFIG_4xx) && !defined(CONFIG_440A)
        if (reason & ESR_IMCP) {
                printk("Instruction");
                mtspr(SPRN_ESR, reason & ~ESR_IMCP);
        } else
                printk("Data");
        printk(" machine check in kernel mode.\n");
-
+#elif defined(CONFIG_440A)
+       printk("Machine check in kernel mode.\n");
+       if (reason & ESR_IMCP){
+               printk("Instruction Synchronous Machine Check exception\n");
+               mtspr(SPRN_ESR, reason & ~ESR_IMCP);
+       }
+       else {
+               u32 mcsr = mfspr(SPRN_MCSR);
+               if (mcsr & MCSR_IB)
+                       printk("Instruction Read PLB Error\n");
+               if (mcsr & MCSR_DRB)
+                       printk("Data Read PLB Error\n");
+               if (mcsr & MCSR_DWB)
+                       printk("Data Write PLB Error\n");
+               if (mcsr & MCSR_TLBP)
+                       printk("TLB Parity Error\n");
+               if (mcsr & MCSR_ICP){
+                       flush_instruction_cache();
+                       printk("I-Cache Parity Error\n");
+               }
+               if (mcsr & MCSR_DCSP)
+                       printk("D-Cache Search Parity Error\n");
+               if (mcsr & MCSR_DCFP)
+                       printk("D-Cache Flush Parity Error\n");
+               if (mcsr & MCSR_IMPE)
+                       printk("Machine Check exception is imprecise\n");
+
+               /* Clear MCSR */
+               mtspr(SPRN_MCSR, mcsr);
+       }
 #else /* !CONFIG_4xx */
        printk("Machine check in kernel mode.\n");
        printk("Caused by (from SRR1=%lx): ", reason);
@@ -605,17 +631,54 @@ TAUException(struct pt_regs *regs)
 }
 #endif /* CONFIG_INT_TAU */
 
+void AltivecUnavailException(struct pt_regs *regs)
+{
+       static int kernel_altivec_count;
+
+#ifndef CONFIG_ALTIVEC
+       if (user_mode(regs)) {
+               /* A user program has executed an altivec instruction,
+                  but this kernel doesn't support altivec. */
+               _exception(SIGILL, regs, ILL_ILLOPC, regs->nip);
+               return;
+       }
+#endif
+       /* The kernel has executed an altivec instruction without
+          first enabling altivec.  Whinge but let it do it. */
+       if (++kernel_altivec_count < 10)
+               printk(KERN_ERR "AltiVec used in kernel (task=%p, pc=%x)\n",
+                      current, regs->nip);
+       regs->msr |= MSR_VEC;
+}
+
 #ifdef CONFIG_ALTIVEC
 void
 AltivecAssistException(struct pt_regs *regs)
 {
+       int err;
+
        preempt_disable();
        if (regs->msr & MSR_VEC)
                giveup_altivec(current);
        preempt_enable();
 
-       /* XXX quick hack for now: set the non-Java bit in the VSCR */
-       current->thread.vscr.u[3] |= 0x10000;
+       err = emulate_altivec(regs);
+       if (err == 0) {
+               regs->nip += 4;         /* skip emulated instruction */
+               emulate_single_step(regs);
+               return;
+       }
+
+       if (err == -EFAULT) {
+               /* got an error reading the instruction */
+               _exception(SIGSEGV, regs, SEGV_ACCERR, regs->nip);
+       } else {
+               /* didn't recognize the instruction */
+               /* XXX quick hack for now: set the non-Java bit in the VSCR */
+               printk(KERN_ERR "unrecognized altivec instruction "
+                      "in %s at %lx\n", current->comm, regs->nip);
+               current->thread.vscr.u[3] |= 0x10000;
+       }
 }
 #endif /* CONFIG_ALTIVEC */