patch-2_6_7-vs1_9_1_12

[linux-2.6.git] / arch / ppc / platforms / 4xx / ocotea.h

diff --git a/arch/ppc/platforms/4xx/ocotea.h b/arch/ppc/platforms/4xx/ocotea.h
index 2f2b5ab..17fe8da 100644 (file)
--- a/arch/ppc/platforms/4xx/ocotea.h
+++ b/arch/ppc/platforms/4xx/ocotea.h
@@ -25,9 +25,9 @@
 #define PPC44x_EMAC0_MR0       0xE0000800
 
 /* Location of MAC addresses in firmware */
-#define OCOTEA_MAC_BASE                (OCOTEA_SMALL_FLASH_HIGH+0xc0500)
+#define OCOTEA_MAC_BASE                (OCOTEA_SMALL_FLASH_HIGH+0xb0500)
 #define OCOTEA_MAC_SIZE                0x200
-#define OCOTEA_MAC1_OFFSET     0x100
+#define OCOTEA_MAC_OFFSET      0x100
 
 /* Default clock rate */
 #define OCOTEA_SYSCLK          25000000
@@ -37,7 +37,7 @@
 #define OCOTEA_RTC_SIZE                0x2000
 
 /* Flash */
-#define OCOTEA_FPGA_ADDR               0x0000000148300000ULL
+#define OCOTEA_FPGA_REG_0              0x0000000148300000ULL
 #define OCOTEA_BOOT_LARGE_FLASH(x)     (x & 0x40)
 #define OCOTEA_SMALL_FLASH_LOW         0x00000001ff900000ULL
 #define OCOTEA_SMALL_FLASH_HIGH                0x00000001fff00000ULL
@@ -46,6 +46,9 @@
 #define OCOTEA_LARGE_FLASH_HIGH                0x00000001ffc00000ULL
 #define OCOTEA_LARGE_FLASH_SIZE                0x400000
 
+/* FPGA_REG_3 (Ethernet Groups) */
+#define OCOTEA_FPGA_REG_3              0x0000000148300003ULL
+
 /*
  * Serial port defines
  */
@@ -57,7 +60,7 @@
 
 #define BASE_BAUD      11059200/16
 #define STD_UART_OP(num)                                       \
-       { 0, BASE_BAUD, 0, UART##num##_IRQ,                     \
+       { 0, BASE_BAUD, 0, UART##num##_INT,                     \
                (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST),        \
                iomem_base: UART##num##_IO_BASE,                \
                io_type: SERIAL_IO_MEM},