fedora core 6 1.2949 + vserver 2.2.0

[linux-2.6.git] / arch / ppc / platforms / 85xx / mpc8560_ads.c

diff --git a/arch/ppc/platforms/85xx/mpc8560_ads.c b/arch/ppc/platforms/85xx/mpc8560_ads.c
index 442c7ff..3a06046 100644 (file)
--- a/arch/ppc/platforms/85xx/mpc8560_ads.c
+++ b/arch/ppc/platforms/85xx/mpc8560_ads.c
@@ -1,6 +1,4 @@
 /*
- * arch/ppc/platforms/85xx/mpc8560_ads.c
- *
  * MPC8560ADS board specific routines
  *
  * Maintainer: Kumar Gala <galak@kernel.crashing.org>
@@ -13,7 +11,6 @@
  * option) any later version.
  */
 
-#include <linux/config.h>
 #include <linux/stddef.h>
 #include <linux/kernel.h>
 #include <linux/init.h>
@@ -32,6 +29,7 @@
 #include <linux/initrd.h>
 #include <linux/module.h>
 #include <linux/fsl_devices.h>
+#include <linux/fs_enet_pd.h>
 
 #include <asm/system.h>
 #include <asm/pgtable.h>
@@ -61,6 +59,71 @@
  * Setup the architecture
  *
  */
+static void init_fcc_ioports(void)
+{
+       struct immap *immap;
+       struct io_port *io;
+       u32 tempval;
+
+       immap = cpm2_immr;
+
+       io = &immap->im_ioport;
+       /* FCC2/3 are on the ports B/C. */
+       tempval = in_be32(&io->iop_pdirb);
+       tempval &= ~PB2_DIRB0;
+       tempval |= PB2_DIRB1;
+       out_be32(&io->iop_pdirb, tempval);
+
+       tempval = in_be32(&io->iop_psorb);
+       tempval &= ~PB2_PSORB0;
+       tempval |= PB2_PSORB1;
+       out_be32(&io->iop_psorb, tempval);
+
+       tempval = in_be32(&io->iop_pparb);
+       tempval |= (PB2_DIRB0 | PB2_DIRB1);
+       out_be32(&io->iop_pparb, tempval);
+
+       tempval = in_be32(&io->iop_pdirb);
+       tempval &= ~PB3_DIRB0;
+       tempval |= PB3_DIRB1;
+       out_be32(&io->iop_pdirb, tempval);
+
+       tempval = in_be32(&io->iop_psorb);
+       tempval &= ~PB3_PSORB0;
+       tempval |= PB3_PSORB1;
+       out_be32(&io->iop_psorb, tempval);
+
+       tempval = in_be32(&io->iop_pparb);
+       tempval |= (PB3_DIRB0 | PB3_DIRB1);
+       out_be32(&io->iop_pparb, tempval);
+
+        tempval = in_be32(&io->iop_pdirc);
+        tempval |= PC3_DIRC1;
+        out_be32(&io->iop_pdirc, tempval);
+
+        tempval = in_be32(&io->iop_pparc);
+        tempval |= PC3_DIRC1;
+        out_be32(&io->iop_pparc, tempval);
+
+       /* Port C has clocks......  */
+       tempval = in_be32(&io->iop_psorc);
+       tempval &= ~(CLK_TRX);
+       out_be32(&io->iop_psorc, tempval);
+
+       tempval = in_be32(&io->iop_pdirc);
+       tempval &= ~(CLK_TRX);
+       out_be32(&io->iop_pdirc, tempval);
+       tempval = in_be32(&io->iop_pparc);
+       tempval |= (CLK_TRX);
+       out_be32(&io->iop_pparc, tempval);
+
+       /* Configure Serial Interface clock routing.
+        * First,  clear all FCC bits to zero,
+        * then set the ones we want.
+        */
+       immap->im_cpmux.cmx_fcr &= ~(CPMUX_CLK_MASK);
+       immap->im_cpmux.cmx_fcr |= CPMUX_CLK_ROUTE;
+}
 
 static void __init
 mpc8560ads_setup_arch(void)
@@ -69,6 +132,7 @@ mpc8560ads_setup_arch(void)
        unsigned int freq;
        struct gianfar_platform_data *pdata;
        struct gianfar_mdio_data *mdata;
+       struct fs_platform_info *fpi;
 
        cpm2_reset();
 
@@ -92,9 +156,9 @@ mpc8560ads_setup_arch(void)
 
        mdata->irq[0] = MPC85xx_IRQ_EXT5;
        mdata->irq[1] = MPC85xx_IRQ_EXT5;
-       mdata->irq[2] = -1;
+       mdata->irq[2] = PHY_POLL;
        mdata->irq[3] = MPC85xx_IRQ_EXT5;
-       mdata->irq[31] = -1;
+       mdata->irq[31] = PHY_POLL;
 
        /* setup the board related information for the enet controllers */
        pdata = (struct gianfar_platform_data *) ppc_sys_get_pdata(MPC85xx_TSEC1);
@@ -113,6 +177,28 @@ mpc8560ads_setup_arch(void)
                memcpy(pdata->mac_addr, binfo->bi_enet1addr, 6);
        }
 
+       init_fcc_ioports();
+       ppc_sys_device_remove(MPC85xx_CPM_FCC1);
+
+       fpi = (struct fs_platform_info *) ppc_sys_get_pdata(MPC85xx_CPM_FCC2);
+       if (fpi) {
+               memcpy(fpi->macaddr, binfo->bi_enet2addr, 6);
+               fpi->bus_id = "0:02";
+               fpi->phy_addr = 2;
+               fpi->dpram_offset = (u32)cpm2_immr->im_dprambase;
+               fpi->fcc_regs_c = (u32)&cpm2_immr->im_fcc_c[1];
+       }
+
+       fpi = (struct fs_platform_info *) ppc_sys_get_pdata(MPC85xx_CPM_FCC3);
+       if (fpi) {
+               memcpy(fpi->macaddr, binfo->bi_enet2addr, 6);
+               fpi->macaddr[5] += 1;
+               fpi->bus_id = "0:03";
+               fpi->phy_addr = 3;
+               fpi->dpram_offset = (u32)cpm2_immr->im_dprambase;
+               fpi->fcc_regs_c = (u32)&cpm2_immr->im_fcc_c[2];
+       }
+
 #ifdef CONFIG_BLK_DEV_INITRD
        if (initrd_start)
                ROOT_DEV = Root_RAM0;
@@ -125,16 +211,16 @@ mpc8560ads_setup_arch(void)
 #endif
 }
 
-static irqreturn_t cpm2_cascade(int irq, void *dev_id, struct pt_regs *regs)
+static irqreturn_t cpm2_cascade(int irq, void *dev_id)
 {
-       while ((irq = cpm2_get_irq(regs)) >= 0)
-               __do_IRQ(irq, regs);
+       while ((irq = cpm2_get_irq()) >= 0)
+               __do_IRQ(irq);
        return IRQ_HANDLED;
 }
 
 static struct irqaction cpm2_irqaction = {
        .handler = cpm2_cascade,
-       .flags = SA_INTERRUPT,
+       .flags = IRQF_DISABLED,
        .mask = CPU_MASK_NONE,
        .name = "cpm2_cascade",
 };