/*
* Set the HID0 and MSR for sleep.
*/
- mfspr r2,HID0
+ mfspr r2,SPRN_HID0
rlwinm r2,r2,0,10,7 /* clear doze, nap */
oris r2,r2,HID0_SLEEP@h
sync
isync
- mtspr HID0,r2
+ mtspr SPRN_HID0,r2
sync
/* This loop puts us back to sleep in case we have a spurrious
/* Make sure HID0 no longer contains any sleep bit and that data cache
* is disabled
*/
- mfspr r3,HID0
+ mfspr r3,SPRN_HID0
rlwinm r3,r3,0,11,7 /* clear SLEEP, NAP, DOZE bits */
rlwinm 3,r3,0,18,15 /* clear DCE, ICE */
- mtspr HID0,r3
+ mtspr SPRN_HID0,r3
sync
isync
/* Restore various CPU config stuffs */
bl __restore_cpu_setup
+ /* Make sure all FPRs have been initialized */
+ bl reloc_offset
+ bl __init_fpu_registers
+
/* Invalidate & enable L1 cache, we don't care about
* whatever the ROM may have tried to write to memory
*/