linux 2.6.16.38 w/ vs2.0.3-rc1

[linux-2.6.git] / arch / ppc / syslib / m8xx_setup.c

diff --git a/arch/ppc/syslib/m8xx_setup.c b/arch/ppc/syslib/m8xx_setup.c
index 54303a7..688616d 100644 (file)
--- a/arch/ppc/syslib/m8xx_setup.c
+++ b/arch/ppc/syslib/m8xx_setup.c
@@ -1,4 +1,6 @@
 /*
+ *  arch/ppc/kernel/setup.c
+ *
  *  Copyright (C) 1995  Linus Torvalds
  *  Adapted from 'alpha' version by Gary Thomas
  *  Modified by Cort Dougan (cort@cs.nmt.edu)
@@ -10,6 +12,7 @@
  * bootup setup stuff..
  */
 
+#include <linux/config.h>
 #include <linux/errno.h>
 #include <linux/sched.h>
 #include <linux/kernel.h>
@@ -31,13 +34,6 @@
 #include <linux/seq_file.h>
 #include <linux/root_dev.h>
 
-#if defined(CONFIG_MTD) && defined(CONFIG_MTD_PHYSMAP)
-#include <linux/mtd/partitions.h>
-#include <linux/mtd/physmap.h>
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/map.h>
-#endif
-
 #include <asm/mmu.h>
 #include <asm/reg.h>
 #include <asm/residual.h>
@@ -53,34 +49,6 @@
 
 #include "ppc8xx_pic.h"
 
-#ifdef CONFIG_MTD_PHYSMAP
-#define MPC8xxADS_BANK_WIDTH 4
-#endif
-
-#define MPC8xxADS_U_BOOT_SIZE          0x80000
-#define MPC8xxADS_FREE_AREA_OFFSET     MPC8xxADS_U_BOOT_SIZE
-
-#if defined(CONFIG_MTD_PARTITIONS)
- /*
-   NOTE: bank width and interleave relative to the installed flash
-   should have been chosen within MTD_CFI_GEOMETRY options.
- */
-static struct mtd_partition mpc8xxads_partitions[] = {
-       {
-               .name = "bootloader",
-               .size = MPC8xxADS_U_BOOT_SIZE,
-               .offset = 0,
-               .mask_flags   = MTD_WRITEABLE,  /* force read-only */
-       }, {
-               .name = "User FS",
-               .offset = MPC8xxADS_FREE_AREA_OFFSET
-       }
-};
-
-#define mpc8xxads_part_num (sizeof (mpc8xxads_partitions) / sizeof (mpc8xxads_partitions[0]))
-
-#endif
-
 static int m8xx_set_rtc_time(unsigned long time);
 static unsigned long m8xx_get_rtc_time(void);
 void m8xx_calibrate_decr(void);
@@ -103,10 +71,6 @@ board_init(void)
 void __init
 m8xx_setup_arch(void)
 {
-#if defined(CONFIG_MTD) && defined(CONFIG_MTD_PHYSMAP)
-       bd_t *binfo = (bd_t *)__res;
-#endif
-
        /* Reset the Communication Processor Module.
        */
        m8xx_cpm_reset();
@@ -142,17 +106,6 @@ m8xx_setup_arch(void)
        }
 #endif
 #endif
-
-#if defined (CONFIG_MPC86XADS) || defined (CONFIG_MPC885ADS)
-#if defined(CONFIG_MTD_PHYSMAP)
-       physmap_configure(binfo->bi_flashstart, binfo->bi_flashsize,
-                                               MPC8xxADS_BANK_WIDTH, NULL);
-#ifdef CONFIG_MTD_PARTITIONS
-       physmap_set_partitions(mpc8xxads_partitions, mpc8xxads_part_num);
-#endif /* CONFIG_MTD_PARTITIONS */
-#endif /* CONFIG_MTD_PHYSMAP */
-#endif
-
        board_init();
 }
 
@@ -187,11 +140,9 @@ void __init __attribute__ ((weak))
 init_internal_rtc(void)
 {
        /* Disable the RTC one second and alarm interrupts. */
-       clrbits16(&((immap_t *)IMAP_ADDR)->im_sit.sit_rtcsc, (RTCSC_SIE | RTCSC_ALE));
-
+       out_be16(&((immap_t *)IMAP_ADDR)->im_sit.sit_rtcsc, in_be16(&((immap_t *)IMAP_ADDR)->im_sit.sit_rtcsc) & ~(RTCSC_SIE | RTCSC_ALE));
        /* Enable the RTC */
-       setbits16(&((immap_t *)IMAP_ADDR)->im_sit.sit_rtcsc, (RTCSC_RTF | RTCSC_RTE));
-
+       out_be16(&((immap_t *)IMAP_ADDR)->im_sit.sit_rtcsc, in_be16(&((immap_t *)IMAP_ADDR)->im_sit.sit_rtcsc) | (RTCSC_RTF | RTCSC_RTE));
 }
 
 /* The decrementer counts at the system (internal) clock frequency divided by
@@ -208,7 +159,8 @@ void __init m8xx_calibrate_decr(void)
        out_be32(&((immap_t *)IMAP_ADDR)->im_clkrstk.cark_sccrk, KAPWR_KEY);
 
        /* Force all 8xx processors to use divide by 16 processor clock. */
-       setbits32(&((immap_t *)IMAP_ADDR)->im_clkrst.car_sccr, 0x02000000);
+       out_be32(&((immap_t *)IMAP_ADDR)->im_clkrst.car_sccr,
+               in_be32(&((immap_t *)IMAP_ADDR)->im_clkrst.car_sccr)|0x02000000);
        /* Processor frequency is MHz.
         * The value 'fp' is the number of decrementer ticks per second.
         */
@@ -287,8 +239,8 @@ m8xx_restart(char *cmd)
        __volatile__ unsigned char dummy;
 
        local_irq_disable();
+       out_be32(&((immap_t *)IMAP_ADDR)->im_clkrst.car_plprcr, in_be32(&((immap_t *)IMAP_ADDR)->im_clkrst.car_plprcr) | 0x00000080);
 
-       setbits32(&((immap_t *)IMAP_ADDR)->im_clkrst.car_plprcr, 0x00000080);
        /* Clear the ME bit in MSR to cause checkstop on machine check
        */
        mtmsr(mfmsr() & ~0x1000);
@@ -346,20 +298,20 @@ m8xx_init_IRQ(void)
        int i;
 
        for (i = SIU_IRQ_OFFSET ; i < SIU_IRQ_OFFSET + NR_SIU_INTS ; i++)
-               irq_desc[i].chip = &ppc8xx_pic;
+               irq_desc[i].handler = &ppc8xx_pic;
 
        cpm_interrupt_init();
 
 #if defined(CONFIG_PCI)
        for (i = I8259_IRQ_OFFSET ; i < I8259_IRQ_OFFSET + NR_8259_INTS ; i++)
-               irq_desc[i].chip = &i8259_pic;
+               irq_desc[i].handler = &i8259_pic;
 
        i8259_pic_irq_offset = I8259_IRQ_OFFSET;
        i8259_init(0);
 
        /* The i8259 cascade interrupt must be level sensitive. */
+       out_be32(&((immap_t *)IMAP_ADDR)->im_siu_conf.sc_siel, in_be32(&((immap_t *)IMAP_ADDR)->im_siu_conf.sc_siel & ~(0x80000000 >> ISA_BRIDGE_INT)));
 
-       clrbits32(&((immap_t *)IMAP_ADDR)->im_siu_conf.sc_siel, (0x80000000 >> ISA_BRIDGE_INT));
        if (setup_irq(ISA_BRIDGE_INT, &mbx_i8259_irqaction))
                enable_irq(ISA_BRIDGE_INT);
 #endif /* CONFIG_PCI */