/*
- * arch/ppc/kernel/ppc4xx_dma.c
+ * Author: Pete Popov <ppopov@mvista.com> or source@mvista.com
*
- * IBM PPC4xx DMA engine core library
+ * arch/ppc/kernel/ppc405_dma.c
*
- * Copyright 2000-2004 MontaVista Software Inc.
+ * 2000 (c) MontaVista, Software, Inc. This file is licensed under
+ * the terms of the GNU General Public License version 2. This program
+ * is licensed "as is" without any warranty of any kind, whether express
+ * or implied.
*
- * Cleaned up and converted to new DCR access
- * Matt Porter <mporter@kernel.crashing.org>
- *
- * Original code by Armin Kuster <akuster@mvista.com>
- * and Pete Popov <ppopov@mvista.com>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 675 Mass Ave, Cambridge, MA 02139, USA.
+ * IBM 405 DMA Controller Functions
*/
#include <linux/config.h>
#include <linux/kernel.h>
+#include <asm/system.h>
+#include <asm/io.h>
#include <linux/mm.h>
#include <linux/miscdevice.h>
#include <linux/init.h>
#include <linux/module.h>
-#include <asm/system.h>
-#include <asm/io.h>
-#include <asm/ppc4xx_dma.h>
-
-ppc_dma_ch_t dma_channels[MAX_PPC4xx_DMA_CHANNELS];
-
-int
-ppc4xx_get_dma_status(void)
-{
- return (mfdcr(DCRN_DMASR));
-}
-
-void
-ppc4xx_set_src_addr(int dmanr, phys_addr_t src_addr)
-{
- if (dmanr >= MAX_PPC4xx_DMA_CHANNELS) {
- printk("set_src_addr: bad channel: %d\n", dmanr);
- return;
- }
-
-#ifdef PPC4xx_DMA64BIT
- mtdcr(DCRN_DMASAH0 + dmanr*2, (u32)(src_addr >> 32));
-#else
- mtdcr(DCRN_DMASA0 + dmanr*2, (u32)src_addr);
-#endif
-}
-
-void
-ppc4xx_set_dst_addr(int dmanr, phys_addr_t dst_addr)
-{
- if (dmanr >= MAX_PPC4xx_DMA_CHANNELS) {
- printk("set_dst_addr: bad channel: %d\n", dmanr);
- return;
- }
-
-#ifdef PPC4xx_DMA64BIT
- mtdcr(DCRN_DMADAH0 + dmanr*2, (u32)(dst_addr >> 32));
-#else
- mtdcr(DCRN_DMADA0 + dmanr*2, (u32)dst_addr);
-#endif
-}
-
-void
-ppc4xx_enable_dma(unsigned int dmanr)
-{
- unsigned int control;
- ppc_dma_ch_t *p_dma_ch = &dma_channels[dmanr];
- unsigned int status_bits[] = { DMA_CS0 | DMA_TS0 | DMA_CH0_ERR,
- DMA_CS1 | DMA_TS1 | DMA_CH1_ERR,
- DMA_CS2 | DMA_TS2 | DMA_CH2_ERR,
- DMA_CS3 | DMA_TS3 | DMA_CH3_ERR};
-
- if (p_dma_ch->in_use) {
- printk("enable_dma: channel %d in use\n", dmanr);
- return;
- }
-
- if (dmanr >= MAX_PPC4xx_DMA_CHANNELS) {
- printk("enable_dma: bad channel: %d\n", dmanr);
- return;
- }
-
- if (p_dma_ch->mode == DMA_MODE_READ) {
- /* peripheral to memory */
- ppc4xx_set_src_addr(dmanr, 0);
- ppc4xx_set_dst_addr(dmanr, p_dma_ch->addr);
- } else if (p_dma_ch->mode == DMA_MODE_WRITE) {
- /* memory to peripheral */
- ppc4xx_set_src_addr(dmanr, p_dma_ch->addr);
- ppc4xx_set_dst_addr(dmanr, 0);
- }
-
- /* for other xfer modes, the addresses are already set */
- control = mfdcr(DCRN_DMACR0 + (dmanr * 0x8));
-
- control &= ~(DMA_TM_MASK | DMA_TD); /* clear all mode bits */
- if (p_dma_ch->mode == DMA_MODE_MM) {
- /* software initiated memory to memory */
- control |= DMA_ETD_OUTPUT | DMA_TCE_ENABLE;
- }
-
- mtdcr(DCRN_DMACR0 + (dmanr * 0x8), control);
-
- /*
- * Clear the CS, TS, RI bits for the channel from DMASR. This
- * has been observed to happen correctly only after the mode and
- * ETD/DCE bits in DMACRx are set above. Must do this before
- * enabling the channel.
- */
-
- mtdcr(DCRN_DMASR, status_bits[dmanr]);
-
- /*
- * For device-paced transfers, Terminal Count Enable apparently
- * must be on, and this must be turned on after the mode, etc.
- * bits are cleared above (at least on Redwood-6).
- */
-
- if ((p_dma_ch->mode == DMA_MODE_MM_DEVATDST) ||
- (p_dma_ch->mode == DMA_MODE_MM_DEVATSRC))
- control |= DMA_TCE_ENABLE;
-
- /*
- * Now enable the channel.
- */
-
- control |= (p_dma_ch->mode | DMA_CE_ENABLE);
-
- mtdcr(DCRN_DMACR0 + (dmanr * 0x8), control);
-
- p_dma_ch->in_use = 1;
-}
-
-void
-ppc4xx_disable_dma(unsigned int dmanr)
-{
- unsigned int control;
- ppc_dma_ch_t *p_dma_ch = &dma_channels[dmanr];
-
- if (!p_dma_ch->in_use) {
- printk("disable_dma: channel %d not in use\n", dmanr);
- return;
- }
-
- if (dmanr >= MAX_PPC4xx_DMA_CHANNELS) {
- printk("disable_dma: bad channel: %d\n", dmanr);
- return;
- }
-
- control = mfdcr(DCRN_DMACR0 + (dmanr * 0x8));
- control &= ~DMA_CE_ENABLE;
- mtdcr(DCRN_DMACR0 + (dmanr * 0x8), control);
-
- p_dma_ch->in_use = 0;
-}
-
-/*
- * Sets the dma mode for single DMA transfers only.
- * For scatter/gather transfers, the mode is passed to the
- * alloc_dma_handle() function as one of the parameters.
- *
- * The mode is simply saved and used later. This allows
- * the driver to call set_dma_mode() and set_dma_addr() in
- * any order.
- *
- * Valid mode values are:
- *
- * DMA_MODE_READ peripheral to memory
- * DMA_MODE_WRITE memory to peripheral
- * DMA_MODE_MM memory to memory
- * DMA_MODE_MM_DEVATSRC device-paced memory to memory, device at src
- * DMA_MODE_MM_DEVATDST device-paced memory to memory, device at dst
- */
-int
-ppc4xx_set_dma_mode(unsigned int dmanr, unsigned int mode)
-{
- ppc_dma_ch_t *p_dma_ch = &dma_channels[dmanr];
-
- if (dmanr >= MAX_PPC4xx_DMA_CHANNELS) {
- printk("set_dma_mode: bad channel 0x%x\n", dmanr);
- return DMA_STATUS_BAD_CHANNEL;
- }
-
- p_dma_ch->mode = mode;
-
- return DMA_STATUS_GOOD;
-}
-
-/*
- * Sets the DMA Count register. Note that 'count' is in bytes.
- * However, the DMA Count register counts the number of "transfers",
- * where each transfer is equal to the bus width. Thus, count
- * MUST be a multiple of the bus width.
- */
-void
-ppc4xx_set_dma_count(unsigned int dmanr, unsigned int count)
-{
- ppc_dma_ch_t *p_dma_ch = &dma_channels[dmanr];
-
-#ifdef DEBUG_4xxDMA
- {
- int error = 0;
- switch (p_dma_ch->pwidth) {
- case PW_8:
- break;
- case PW_16:
- if (count & 0x1)
- error = 1;
- break;
- case PW_32:
- if (count & 0x3)
- error = 1;
- break;
- case PW_64:
- if (count & 0x7)
- error = 1;
- break;
- default:
- printk("set_dma_count: invalid bus width: 0x%x\n",
- p_dma_ch->pwidth);
- return;
- }
- if (error)
- printk
- ("Warning: set_dma_count count 0x%x bus width %d\n",
- count, p_dma_ch->pwidth);
- }
-#endif
+#include <asm/ppc405_dma.h>
- count = count >> p_dma_ch->shift;
-
- mtdcr(DCRN_DMACT0 + (dmanr * 0x8), count);
-}
/*
- * Returns the number of bytes left to be transfered.
- * After a DMA transfer, this should return zero.
- * Reading this while a DMA transfer is still in progress will return
- * unpredictable results.
+ * Function prototypes
*/
-int
-ppc4xx_get_dma_residue(unsigned int dmanr)
-{
- unsigned int count;
- ppc_dma_ch_t *p_dma_ch = &dma_channels[dmanr];
- if (dmanr >= MAX_PPC4xx_DMA_CHANNELS) {
- printk("ppc4xx_get_dma_residue: bad channel 0x%x\n", dmanr);
- return DMA_STATUS_BAD_CHANNEL;
- }
+int hw_init_dma_channel(unsigned int, ppc_dma_ch_t *);
+int init_dma_channel(unsigned int);
+int get_channel_config(unsigned int, ppc_dma_ch_t *);
+int set_channel_priority(unsigned int, unsigned int);
+unsigned int get_peripheral_width(unsigned int);
+int alloc_dma_handle(sgl_handle_t *, unsigned int, unsigned int);
+void free_dma_handle(sgl_handle_t);
- count = mfdcr(DCRN_DMACT0 + (dmanr * 0x8));
- return (count << p_dma_ch->shift);
-}
-
-/*
- * Sets the DMA address for a memory to peripheral or peripheral
- * to memory transfer. The address is just saved in the channel
- * structure for now and used later in enable_dma().
- */
-void
-ppc4xx_set_dma_addr(unsigned int dmanr, phys_addr_t addr)
-{
- ppc_dma_ch_t *p_dma_ch = &dma_channels[dmanr];
-
- if (dmanr >= MAX_PPC4xx_DMA_CHANNELS) {
- printk("ppc4xx_set_dma_addr: bad channel: %d\n", dmanr);
- return;
- }
-
-#ifdef DEBUG_4xxDMA
- {
- int error = 0;
- switch (p_dma_ch->pwidth) {
- case PW_8:
- break;
- case PW_16:
- if ((unsigned) addr & 0x1)
- error = 1;
- break;
- case PW_32:
- if ((unsigned) addr & 0x3)
- error = 1;
- break;
- case PW_64:
- if ((unsigned) addr & 0x7)
- error = 1;
- break;
- default:
- printk("ppc4xx_set_dma_addr: invalid bus width: 0x%x\n",
- p_dma_ch->pwidth);
- return;
- }
- if (error)
- printk("Warning: ppc4xx_set_dma_addr addr 0x%x bus width %d\n",
- addr, p_dma_ch->pwidth);
- }
-#endif
-
- /* save dma address and program it later after we know the xfer mode */
- p_dma_ch->addr = addr;
-}
-
-/*
- * Sets both DMA addresses for a memory to memory transfer.
- * For memory to peripheral or peripheral to memory transfers
- * the function set_dma_addr() should be used instead.
- */
-void
-ppc4xx_set_dma_addr2(unsigned int dmanr, phys_addr_t src_dma_addr,
- phys_addr_t dst_dma_addr)
-{
- if (dmanr >= MAX_PPC4xx_DMA_CHANNELS) {
- printk("ppc4xx_set_dma_addr2: bad channel: %d\n", dmanr);
- return;
- }
-
-#ifdef DEBUG_4xxDMA
- {
- ppc_dma_ch_t *p_dma_ch = &dma_channels[dmanr];
- int error = 0;
- switch (p_dma_ch->pwidth) {
- case PW_8:
- break;
- case PW_16:
- if (((unsigned) src_dma_addr & 0x1) ||
- ((unsigned) dst_dma_addr & 0x1)
- )
- error = 1;
- break;
- case PW_32:
- if (((unsigned) src_dma_addr & 0x3) ||
- ((unsigned) dst_dma_addr & 0x3)
- )
- error = 1;
- break;
- case PW_64:
- if (((unsigned) src_dma_addr & 0x7) ||
- ((unsigned) dst_dma_addr & 0x7)
- )
- error = 1;
- break;
- default:
- printk("ppc4xx_set_dma_addr2: invalid bus width: 0x%x\n",
- p_dma_ch->pwidth);
- return;
- }
- if (error)
- printk
- ("Warning: ppc4xx_set_dma_addr2 src 0x%x dst 0x%x bus width %d\n",
- src_dma_addr, dst_dma_addr, p_dma_ch->pwidth);
- }
-#endif
-
- ppc4xx_set_src_addr(dmanr, src_dma_addr);
- ppc4xx_set_dst_addr(dmanr, dst_dma_addr);
-}
-
-/*
- * Enables the channel interrupt.
- *
- * If performing a scatter/gatter transfer, this function
- * MUST be called before calling alloc_dma_handle() and building
- * the sgl list. Otherwise, interrupts will not be enabled, if
- * they were previously disabled.
- */
-int
-ppc4xx_enable_dma_interrupt(unsigned int dmanr)
-{
- unsigned int control;
- ppc_dma_ch_t *p_dma_ch = &dma_channels[dmanr];
-
- if (dmanr >= MAX_PPC4xx_DMA_CHANNELS) {
- printk("ppc4xx_enable_dma_interrupt: bad channel: %d\n", dmanr);
- return DMA_STATUS_BAD_CHANNEL;
- }
-
- p_dma_ch->int_enable = 1;
-
- control = mfdcr(DCRN_DMACR0 + (dmanr * 0x8));
- control |= DMA_CIE_ENABLE; /* Channel Interrupt Enable */
- mtdcr(DCRN_DMACR0 + (dmanr * 0x8), control);
-
- return DMA_STATUS_GOOD;
-}
-
-/*
- * Disables the channel interrupt.
- *
- * If performing a scatter/gatter transfer, this function
- * MUST be called before calling alloc_dma_handle() and building
- * the sgl list. Otherwise, interrupts will not be disabled, if
- * they were previously enabled.
- */
-int
-ppc4xx_disable_dma_interrupt(unsigned int dmanr)
-{
- unsigned int control;
- ppc_dma_ch_t *p_dma_ch = &dma_channels[dmanr];
-
- if (dmanr >= MAX_PPC4xx_DMA_CHANNELS) {
- printk("ppc4xx_disable_dma_interrupt: bad channel: %d\n", dmanr);
- return DMA_STATUS_BAD_CHANNEL;
- }
-
- p_dma_ch->int_enable = 0;
-
- control = mfdcr(DCRN_DMACR0 + (dmanr * 0x8));
- control &= ~DMA_CIE_ENABLE; /* Channel Interrupt Enable */
- mtdcr(DCRN_DMACR0 + (dmanr * 0x8), control);
-
- return DMA_STATUS_GOOD;
-}
+ppc_dma_ch_t dma_channels[MAX_405GP_DMA_CHANNELS];
/*
* Configures a DMA channel, including the peripheral bus width, if a
* called from platform specific init code. The driver should not need to
* call this function.
*/
-int
-ppc4xx_init_dma_channel(unsigned int dmanr, ppc_dma_ch_t * p_init)
+int hw_init_dma_channel(unsigned int dmanr, ppc_dma_ch_t *p_init)
{
- unsigned int polarity;
- uint32_t control = 0;
- ppc_dma_ch_t *p_dma_ch = &dma_channels[dmanr];
-
- DMA_MODE_READ = (unsigned long) DMA_TD; /* Peripheral to Memory */
- DMA_MODE_WRITE = 0; /* Memory to Peripheral */
-
- if (!p_init) {
- printk("ppc4xx_init_dma_channel: NULL p_init\n");
- return DMA_STATUS_NULL_POINTER;
- }
-
- if (dmanr >= MAX_PPC4xx_DMA_CHANNELS) {
- printk("ppc4xx_init_dma_channel: bad channel %d\n", dmanr);
- return DMA_STATUS_BAD_CHANNEL;
- }
+ unsigned int polarity;
+ uint32_t control = 0;
+ ppc_dma_ch_t *p_dma_ch = &dma_channels[dmanr];
+
+#ifdef DEBUG_405DMA
+ if (!p_init) {
+ printk("hw_init_dma_channel: NULL p_init\n");
+ return DMA_STATUS_NULL_POINTER;
+ }
+ if (dmanr >= MAX_405GP_DMA_CHANNELS) {
+ printk("hw_init_dma_channel: bad channel %d\n", dmanr);
+ return DMA_STATUS_BAD_CHANNEL;
+ }
+#endif
#if DCRN_POL > 0
- polarity = mfdcr(DCRN_POL);
+ polarity = mfdcr(DCRN_POL);
#else
- polarity = 0;
+ polarity = 0;
#endif
- /* Setup the control register based on the values passed to
- * us in p_init. Then, over-write the control register with this
- * new value.
- */
- control |= SET_DMA_CONTROL;
-
- /* clear all polarity signals and then "or" in new signal levels */
- polarity &= ~GET_DMA_POLARITY(dmanr);
- polarity |= p_dma_ch->polarity;
+ /* Setup the control register based on the values passed to
+ * us in p_init. Then, over-write the control register with this
+ * new value.
+ */
+
+ control |= (
+ SET_DMA_CIE_ENABLE(p_init->int_enable) | /* interrupt enable */
+ SET_DMA_BEN(p_init->buffer_enable) | /* buffer enable */
+ SET_DMA_ETD(p_init->etd_output) | /* end of transfer pin */
+ SET_DMA_TCE(p_init->tce_enable) | /* terminal count enable */
+ SET_DMA_PL(p_init->pl) | /* peripheral location */
+ SET_DMA_DAI(p_init->dai) | /* dest addr increment */
+ SET_DMA_SAI(p_init->sai) | /* src addr increment */
+ SET_DMA_PRIORITY(p_init->cp) | /* channel priority */
+ SET_DMA_PW(p_init->pwidth) | /* peripheral/bus width */
+ SET_DMA_PSC(p_init->psc) | /* peripheral setup cycles */
+ SET_DMA_PWC(p_init->pwc) | /* peripheral wait cycles */
+ SET_DMA_PHC(p_init->phc) | /* peripheral hold cycles */
+ SET_DMA_PREFETCH(p_init->pf) /* read prefetch */
+ );
+
+ switch (dmanr) {
+ case 0:
+ /* clear all polarity signals and then "or" in new signal levels */
+ polarity &= ~(DMAReq0_ActiveLow | DMAAck0_ActiveLow | EOT0_ActiveLow);
+ polarity |= p_dma_ch->polarity;
#if DCRN_POL > 0
- mtdcr(DCRN_POL, polarity);
+ mtdcr(DCRN_POL, polarity);
#endif
- mtdcr(DCRN_DMACR0 + (dmanr * 0x8), control);
-
- /* save these values in our dma channel structure */
- memcpy(p_dma_ch, p_init, sizeof (ppc_dma_ch_t));
-
- /*
- * The peripheral width values written in the control register are:
- * PW_8 0
- * PW_16 1
- * PW_32 2
- * PW_64 3
- *
- * Since the DMA count register takes the number of "transfers",
- * we need to divide the count sent to us in certain
- * functions by the appropriate number. It so happens that our
- * right shift value is equal to the peripheral width value.
- */
- p_dma_ch->shift = p_init->pwidth;
-
- /*
- * Save the control word for easy access.
- */
- p_dma_ch->control = control;
-
- mtdcr(DCRN_DMASR, 0xffffffff); /* clear status register */
- return DMA_STATUS_GOOD;
+ mtdcr(DCRN_DMACR0, control);
+ break;
+ case 1:
+ polarity &= ~(DMAReq1_ActiveLow | DMAAck1_ActiveLow | EOT1_ActiveLow);
+ polarity |= p_dma_ch->polarity;
+#if DCRN_POL > 0
+ mtdcr(DCRN_POL, polarity);
+#endif
+ mtdcr(DCRN_DMACR1, control);
+ break;
+ case 2:
+ polarity &= ~(DMAReq2_ActiveLow | DMAAck2_ActiveLow | EOT2_ActiveLow);
+ polarity |= p_dma_ch->polarity;
+#if DCRN_POL > 0
+ mtdcr(DCRN_POL, polarity);
+#endif
+ mtdcr(DCRN_DMACR2, control);
+ break;
+ case 3:
+ polarity &= ~(DMAReq3_ActiveLow | DMAAck3_ActiveLow | EOT3_ActiveLow);
+ polarity |= p_dma_ch->polarity;
+#if DCRN_POL > 0
+ mtdcr(DCRN_POL, polarity);
+#endif
+ mtdcr(DCRN_DMACR3, control);
+ break;
+ default:
+ return DMA_STATUS_BAD_CHANNEL;
+ }
+
+ /* save these values in our dma channel structure */
+ memcpy(p_dma_ch, p_init, sizeof(ppc_dma_ch_t));
+
+ /*
+ * The peripheral width values written in the control register are:
+ * PW_8 0
+ * PW_16 1
+ * PW_32 2
+ * PW_64 3
+ *
+ * Since the DMA count register takes the number of "transfers",
+ * we need to divide the count sent to us in certain
+ * functions by the appropriate number. It so happens that our
+ * right shift value is equal to the peripheral width value.
+ */
+ p_dma_ch->shift = p_init->pwidth;
+
+ /*
+ * Save the control word for easy access.
+ */
+ p_dma_ch->control = control;
+
+ mtdcr(DCRN_DMASR, 0xffffffff); /* clear status register */
+ return DMA_STATUS_GOOD;
}
+
+
+
/*
* This function returns the channel configuration.
*/
-int
-ppc4xx_get_channel_config(unsigned int dmanr, ppc_dma_ch_t * p_dma_ch)
+int get_channel_config(unsigned int dmanr, ppc_dma_ch_t *p_dma_ch)
{
- unsigned int polarity;
- unsigned int control;
-
- if (dmanr >= MAX_PPC4xx_DMA_CHANNELS) {
- printk("ppc4xx_get_channel_config: bad channel %d\n", dmanr);
- return DMA_STATUS_BAD_CHANNEL;
- }
+ unsigned int polarity;
+ unsigned int control;
#if DCRN_POL > 0
- polarity = mfdcr(DCRN_POL);
+ polarity = mfdcr(DCRN_POL);
#else
- polarity = 0;
+ polarity = 0;
#endif
- p_dma_ch->polarity = polarity & GET_DMA_POLARITY(dmanr);
- control = mfdcr(DCRN_DMACR0 + (dmanr * 0x8));
-
- p_dma_ch->cp = GET_DMA_PRIORITY(control);
- p_dma_ch->pwidth = GET_DMA_PW(control);
- p_dma_ch->psc = GET_DMA_PSC(control);
- p_dma_ch->pwc = GET_DMA_PWC(control);
- p_dma_ch->phc = GET_DMA_PHC(control);
- p_dma_ch->ce = GET_DMA_CE_ENABLE(control);
- p_dma_ch->int_enable = GET_DMA_CIE_ENABLE(control);
- p_dma_ch->shift = GET_DMA_PW(control);
-
-#ifdef CONFIG_PPC4xx_EDMA
- p_dma_ch->pf = GET_DMA_PREFETCH(control);
-#else
- p_dma_ch->ch_enable = GET_DMA_CH(control);
- p_dma_ch->ece_enable = GET_DMA_ECE(control);
- p_dma_ch->tcd_disable = GET_DMA_TCD(control);
-#endif
- return DMA_STATUS_GOOD;
+ switch (dmanr) {
+ case 0:
+ p_dma_ch->polarity =
+ polarity & (DMAReq0_ActiveLow | DMAAck0_ActiveLow | EOT0_ActiveLow);
+ control = mfdcr(DCRN_DMACR0);
+ break;
+ case 1:
+ p_dma_ch->polarity =
+ polarity & (DMAReq1_ActiveLow | DMAAck1_ActiveLow | EOT1_ActiveLow);
+ control = mfdcr(DCRN_DMACR1);
+ break;
+ case 2:
+ p_dma_ch->polarity =
+ polarity & (DMAReq2_ActiveLow | DMAAck2_ActiveLow | EOT2_ActiveLow);
+ control = mfdcr(DCRN_DMACR2);
+ break;
+ case 3:
+ p_dma_ch->polarity =
+ polarity & (DMAReq3_ActiveLow | DMAAck3_ActiveLow | EOT3_ActiveLow);
+ control = mfdcr(DCRN_DMACR3);
+ break;
+ default:
+ return DMA_STATUS_BAD_CHANNEL;
+ }
+
+ p_dma_ch->cp = GET_DMA_PRIORITY(control);
+ p_dma_ch->pwidth = GET_DMA_PW(control);
+ p_dma_ch->psc = GET_DMA_PSC(control);
+ p_dma_ch->pwc = GET_DMA_PWC(control);
+ p_dma_ch->phc = GET_DMA_PHC(control);
+ p_dma_ch->pf = GET_DMA_PREFETCH(control);
+ p_dma_ch->int_enable = GET_DMA_CIE_ENABLE(control);
+ p_dma_ch->shift = GET_DMA_PW(control);
+
+ return DMA_STATUS_GOOD;
}
/*
* PRIORITY_HIGH
*
*/
-int
-ppc4xx_set_channel_priority(unsigned int dmanr, unsigned int priority)
+int set_channel_priority(unsigned int dmanr, unsigned int priority)
{
- unsigned int control;
-
- if (dmanr >= MAX_PPC4xx_DMA_CHANNELS) {
- printk("ppc4xx_set_channel_priority: bad channel %d\n", dmanr);
- return DMA_STATUS_BAD_CHANNEL;
- }
+ unsigned int control;
+
+#ifdef DEBUG_405DMA
+ if ( (priority != PRIORITY_LOW) &&
+ (priority != PRIORITY_MID_LOW) &&
+ (priority != PRIORITY_MID_HIGH) &&
+ (priority != PRIORITY_HIGH)) {
+ printk("set_channel_priority: bad priority: 0x%x\n", priority);
+ }
+#endif
- if ((priority != PRIORITY_LOW) &&
- (priority != PRIORITY_MID_LOW) &&
- (priority != PRIORITY_MID_HIGH) && (priority != PRIORITY_HIGH)) {
- printk("ppc4xx_set_channel_priority: bad priority: 0x%x\n", priority);
- }
+ switch (dmanr) {
+ case 0:
+ control = mfdcr(DCRN_DMACR0);
+ control|= SET_DMA_PRIORITY(priority);
+ mtdcr(DCRN_DMACR0, control);
+ break;
+ case 1:
+ control = mfdcr(DCRN_DMACR1);
+ control|= SET_DMA_PRIORITY(priority);
+ mtdcr(DCRN_DMACR1, control);
+ break;
+ case 2:
+ control = mfdcr(DCRN_DMACR2);
+ control|= SET_DMA_PRIORITY(priority);
+ mtdcr(DCRN_DMACR2, control);
+ break;
+ case 3:
+ control = mfdcr(DCRN_DMACR3);
+ control|= SET_DMA_PRIORITY(priority);
+ mtdcr(DCRN_DMACR3, control);
+ break;
+ default:
+#ifdef DEBUG_405DMA
+ printk("set_channel_priority: bad channel: %d\n", dmanr);
+#endif
+ return DMA_STATUS_BAD_CHANNEL;
+ }
+ return DMA_STATUS_GOOD;
+}
- control = mfdcr(DCRN_DMACR0 + (dmanr * 0x8));
- control |= SET_DMA_PRIORITY(priority);
- mtdcr(DCRN_DMACR0 + (dmanr * 0x8), control);
- return DMA_STATUS_GOOD;
-}
/*
* Returns the width of the peripheral attached to this channel. This assumes
*
* The function returns 0 on error.
*/
-unsigned int
-ppc4xx_get_peripheral_width(unsigned int dmanr)
+unsigned int get_peripheral_width(unsigned int dmanr)
{
- unsigned int control;
+ unsigned int control;
+
+ switch (dmanr) {
+ case 0:
+ control = mfdcr(DCRN_DMACR0);
+ break;
+ case 1:
+ control = mfdcr(DCRN_DMACR1);
+ break;
+ case 2:
+ control = mfdcr(DCRN_DMACR2);
+ break;
+ case 3:
+ control = mfdcr(DCRN_DMACR3);
+ break;
+ default:
+#ifdef DEBUG_405DMA
+ printk("get_peripheral_width: bad channel: %d\n", dmanr);
+#endif
+ return 0;
+ }
+ return(GET_DMA_PW(control));
+}
+
+
+
+
+/*
+ * Create a scatter/gather list handle. This is simply a structure which
+ * describes a scatter/gather list.
+ *
+ * A handle is returned in "handle" which the driver should save in order to
+ * be able to access this list later. A chunk of memory will be allocated
+ * to be used by the API for internal management purposes, including managing
+ * the sg list and allocating memory for the sgl descriptors. One page should
+ * be more than enough for that purpose. Perhaps it's a bit wasteful to use
+ * a whole page for a single sg list, but most likely there will be only one
+ * sg list per channel.
+ *
+ * Interrupt notes:
+ * Each sgl descriptor has a copy of the DMA control word which the DMA engine
+ * loads in the control register. The control word has a "global" interrupt
+ * enable bit for that channel. Interrupts are further qualified by a few bits
+ * in the sgl descriptor count register. In order to setup an sgl, we have to
+ * know ahead of time whether or not interrupts will be enabled at the completion
+ * of the transfers. Thus, enable_dma_interrupt()/disable_dma_interrupt() MUST
+ * be called before calling alloc_dma_handle(). If the interrupt mode will never
+ * change after powerup, then enable_dma_interrupt()/disable_dma_interrupt()
+ * do not have to be called -- interrupts will be enabled or disabled based
+ * on how the channel was configured after powerup by the hw_init_dma_channel()
+ * function. Each sgl descriptor will be setup to interrupt if an error occurs;
+ * however, only the last descriptor will be setup to interrupt. Thus, an
+ * interrupt will occur (if interrupts are enabled) only after the complete
+ * sgl transfer is done.
+ */
+int alloc_dma_handle(sgl_handle_t *phandle, unsigned int mode, unsigned int dmanr)
+{
+ sgl_list_info_t *psgl;
+ dma_addr_t dma_addr;
+ ppc_dma_ch_t *p_dma_ch = &dma_channels[dmanr];
+ uint32_t sg_command;
+ void *ret;
+
+#ifdef DEBUG_405DMA
+ if (!phandle) {
+ printk("alloc_dma_handle: null handle pointer\n");
+ return DMA_STATUS_NULL_POINTER;
+ }
+ switch (mode) {
+ case DMA_MODE_READ:
+ case DMA_MODE_WRITE:
+ case DMA_MODE_MM:
+ case DMA_MODE_MM_DEVATSRC:
+ case DMA_MODE_MM_DEVATDST:
+ break;
+ default:
+ printk("alloc_dma_handle: bad mode 0x%x\n", mode);
+ return DMA_STATUS_BAD_MODE;
+ }
+ if (dmanr >= MAX_405GP_DMA_CHANNELS) {
+ printk("alloc_dma_handle: invalid channel 0x%x\n", dmanr);
+ return DMA_STATUS_BAD_CHANNEL;
+ }
+#endif
- if (dmanr >= MAX_PPC4xx_DMA_CHANNELS) {
- printk("ppc4xx_get_peripheral_width: bad channel %d\n", dmanr);
- return DMA_STATUS_BAD_CHANNEL;
+ /* Get a page of memory, which is zeroed out by pci_alloc_consistent() */
+
+/* wrong not a pci device - armin */
+ /* psgl = (sgl_list_info_t *) pci_alloc_consistent(NULL, SGL_LIST_SIZE, &dma_addr);
+*/
+
+ ret = consistent_alloc(GFP_ATOMIC |GFP_DMA, SGL_LIST_SIZE, &dma_addr);
+ if (ret != NULL) {
+ memset(ret, 0,SGL_LIST_SIZE );
+ psgl = (sgl_list_info_t *) ret;
}
- control = mfdcr(DCRN_DMACR0 + (dmanr * 0x8));
- return (GET_DMA_PW(control));
+ if (psgl == NULL) {
+ *phandle = (sgl_handle_t)NULL;
+ return DMA_STATUS_OUT_OF_MEMORY;
+ }
+
+ psgl->dma_addr = dma_addr;
+ psgl->dmanr = dmanr;
+
+ /*
+ * Modify and save the control word. These word will get written to each sgl
+ * descriptor. The DMA engine then loads this control word into the control
+ * register every time it reads a new descriptor.
+ */
+ psgl->control = p_dma_ch->control;
+ psgl->control &= ~(DMA_TM_MASK | DMA_TD); /* clear all "mode" bits first */
+ psgl->control |= (mode | DMA_CH_ENABLE); /* save the control word along with the mode */
+
+ if (p_dma_ch->int_enable) {
+ psgl->control |= DMA_CIE_ENABLE; /* channel interrupt enabled */
+ }
+ else {
+ psgl->control &= ~DMA_CIE_ENABLE;
+ }
+
+#if DCRN_ASGC > 0
+ sg_command = mfdcr(DCRN_ASGC);
+ switch (dmanr) {
+ case 0:
+ sg_command |= SSG0_MASK_ENABLE;
+ break;
+ case 1:
+ sg_command |= SSG1_MASK_ENABLE;
+ break;
+ case 2:
+ sg_command |= SSG2_MASK_ENABLE;
+ break;
+ case 3:
+ sg_command |= SSG3_MASK_ENABLE;
+ break;
+ default:
+#ifdef DEBUG_405DMA
+ printk("alloc_dma_handle: bad channel: %d\n", dmanr);
+#endif
+ free_dma_handle((sgl_handle_t)psgl);
+ *phandle = (sgl_handle_t)NULL;
+ return DMA_STATUS_BAD_CHANNEL;
+ }
+
+ mtdcr(DCRN_ASGC, sg_command); /* enable writing to this channel's sgl control bits */
+#else
+ (void)sg_command;
+#endif
+ psgl->sgl_control = SG_ERI_ENABLE | SG_LINK; /* sgl descriptor control bits */
+
+ if (p_dma_ch->int_enable) {
+ if (p_dma_ch->tce_enable)
+ psgl->sgl_control |= SG_TCI_ENABLE;
+ else
+ psgl->sgl_control |= SG_ETI_ENABLE;
+ }
+
+ *phandle = (sgl_handle_t)psgl;
+ return DMA_STATUS_GOOD;
+}
+
+
+
+/*
+ * Destroy a scatter/gather list handle that was created by alloc_dma_handle().
+ * The list must be empty (contain no elements).
+ */
+void free_dma_handle(sgl_handle_t handle)
+{
+ sgl_list_info_t *psgl = (sgl_list_info_t *)handle;
+
+ if (!handle) {
+#ifdef DEBUG_405DMA
+ printk("free_dma_handle: got NULL\n");
+#endif
+ return;
+ }
+ else if (psgl->phead) {
+#ifdef DEBUG_405DMA
+ printk("free_dma_handle: list not empty\n");
+#endif
+ return;
+ }
+ else if (!psgl->dma_addr) { /* should never happen */
+#ifdef DEBUG_405DMA
+ printk("free_dma_handle: no dma address\n");
+#endif
+ return;
+ }
+
+ /* wrong not a PCI device -armin */
+ /* pci_free_consistent(NULL, SGL_LIST_SIZE, (void *)psgl, psgl->dma_addr); */
+ // free_pages((unsigned long)psgl, get_order(SGL_LIST_SIZE));
+ consistent_free((void *)psgl);
+
+
}
-EXPORT_SYMBOL(ppc4xx_init_dma_channel);
-EXPORT_SYMBOL(ppc4xx_get_channel_config);
-EXPORT_SYMBOL(ppc4xx_set_channel_priority);
-EXPORT_SYMBOL(ppc4xx_get_peripheral_width);
+EXPORT_SYMBOL(hw_init_dma_channel);
+EXPORT_SYMBOL(get_channel_config);
+EXPORT_SYMBOL(set_channel_priority);
+EXPORT_SYMBOL(get_peripheral_width);
+EXPORT_SYMBOL(alloc_dma_handle);
+EXPORT_SYMBOL(free_dma_handle);
EXPORT_SYMBOL(dma_channels);
-EXPORT_SYMBOL(ppc4xx_set_src_addr);
-EXPORT_SYMBOL(ppc4xx_set_dst_addr);
-EXPORT_SYMBOL(ppc4xx_set_dma_addr);
-EXPORT_SYMBOL(ppc4xx_set_dma_addr2);
-EXPORT_SYMBOL(ppc4xx_enable_dma);
-EXPORT_SYMBOL(ppc4xx_disable_dma);
-EXPORT_SYMBOL(ppc4xx_set_dma_mode);
-EXPORT_SYMBOL(ppc4xx_set_dma_count);
-EXPORT_SYMBOL(ppc4xx_get_dma_residue);
-EXPORT_SYMBOL(ppc4xx_enable_dma_interrupt);
-EXPORT_SYMBOL(ppc4xx_disable_dma_interrupt);
-EXPORT_SYMBOL(ppc4xx_get_dma_status);
git://git.onelab.eu / linux-2.6.git / blobdiff