#define SECONDARY_PROCESSORS
#include <linux/config.h>
+#include <linux/threads.h>
#include <asm/processor.h>
#include <asm/page.h>
#include <asm/mmu.h>
*
* For iSeries:
* 1. The MMU is on (as it always is for iSeries)
- * 2. The kernel is entered at SystemReset_Iseries
+ * 2. The kernel is entered at system_reset_iSeries
*/
.text
#else
#ifdef CONFIG_SMP
mr r3,r24
- b .pseries_secondary_smp_init
+ b .pSeries_secondary_smp_init
#else
BUG_OPCODE
#endif
*/
#define STD_EXCEPTION_PSERIES(n, label) \
. = n; \
- .globl label##_Pseries; \
-label##_Pseries: \
+ .globl label##_pSeries; \
+label##_pSeries: \
HMT_MEDIUM; \
mtspr SPRG1,r13; /* save r13 */ \
EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, label##_common)
#define STD_EXCEPTION_ISERIES(n, label, area) \
- .globl label##_Iseries; \
-label##_Iseries: \
+ .globl label##_iSeries; \
+label##_iSeries: \
HMT_MEDIUM; \
mtspr SPRG1,r13; /* save r13 */ \
EXCEPTION_PROLOG_ISERIES_1(area); \
b label##_common
#define MASKABLE_EXCEPTION_ISERIES(n, label) \
- .globl label##_Iseries; \
-label##_Iseries: \
+ .globl label##_iSeries; \
+label##_iSeries: \
HMT_MEDIUM; \
mtspr SPRG1,r13; /* save r13 */ \
EXCEPTION_PROLOG_ISERIES_1(PACA_EXGEN); \
lbz r10,PACAPROCENABLED(r13); \
cmpwi 0,r10,0; \
- beq- label##_Iseries_masked; \
+ beq- label##_iSeries_masked; \
EXCEPTION_PROLOG_ISERIES_2; \
b label##_common; \
.globl __start_interrupts
__start_interrupts:
- STD_EXCEPTION_PSERIES(0x100, SystemReset)
+ STD_EXCEPTION_PSERIES(0x100, system_reset)
. = 0x200
-_MachineCheckPseries:
+_machine_check_pSeries:
HMT_MEDIUM
mtspr SPRG1,r13 /* save r13 */
- EXCEPTION_PROLOG_PSERIES(PACA_EXMC, MachineCheck_common)
+ EXCEPTION_PROLOG_PSERIES(PACA_EXMC, machine_check_common)
. = 0x300
- .globl DataAccess_Pseries
-DataAccess_Pseries:
+ .globl data_access_pSeries
+data_access_pSeries:
HMT_MEDIUM
mtspr SPRG1,r13
BEGIN_FTR_SECTION
rlwimi r13,r12,16,0x20
mfcr r12
cmpwi r13,0x2c
- beq .do_stab_bolted_Pseries
+ beq .do_stab_bolted_pSeries
mtcrf 0x80,r12
mfspr r12,SPRG2
END_FTR_SECTION_IFCLR(CPU_FTR_SLB)
- EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, DataAccess_common)
+ EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, data_access_common)
. = 0x380
- .globl DataAccessSLB_Pseries
-DataAccessSLB_Pseries:
+ .globl data_access_slb_pSeries
+data_access_slb_pSeries:
HMT_MEDIUM
mtspr SPRG1,r13
mfspr r13,SPRG3 /* get paca address into r13 */
mfspr r3,DAR
b .do_slb_miss /* Rel. branch works in real mode */
- STD_EXCEPTION_PSERIES(0x400, InstructionAccess)
+ STD_EXCEPTION_PSERIES(0x400, instruction_access)
. = 0x480
- .globl InstructionAccessSLB_Pseries
-InstructionAccessSLB_Pseries:
+ .globl instruction_access_slb_pSeries
+instruction_access_slb_pSeries:
HMT_MEDIUM
mtspr SPRG1,r13
mfspr r13,SPRG3 /* get paca address into r13 */
mfspr r3,SRR0 /* SRR0 is faulting address */
b .do_slb_miss /* Rel. branch works in real mode */
- STD_EXCEPTION_PSERIES(0x500, HardwareInterrupt)
- STD_EXCEPTION_PSERIES(0x600, Alignment)
- STD_EXCEPTION_PSERIES(0x700, ProgramCheck)
- STD_EXCEPTION_PSERIES(0x800, FPUnavailable)
- STD_EXCEPTION_PSERIES(0x900, Decrementer)
- STD_EXCEPTION_PSERIES(0xa00, Trap_0a)
- STD_EXCEPTION_PSERIES(0xb00, Trap_0b)
+ STD_EXCEPTION_PSERIES(0x500, hardware_interrupt)
+ STD_EXCEPTION_PSERIES(0x600, alignment)
+ STD_EXCEPTION_PSERIES(0x700, program_check)
+ STD_EXCEPTION_PSERIES(0x800, fp_unavailable)
+ STD_EXCEPTION_PSERIES(0x900, decrementer)
+ STD_EXCEPTION_PSERIES(0xa00, trap_0a)
+ STD_EXCEPTION_PSERIES(0xb00, trap_0b)
. = 0xc00
- .globl SystemCall_Pseries
-SystemCall_Pseries:
+ .globl system_call_pSeries
+system_call_pSeries:
HMT_MEDIUM
mr r9,r13
mfmsr r10
mfspr r13,SPRG3
mfspr r11,SRR0
clrrdi r12,r13,32
- oris r12,r12,SystemCall_common@h
- ori r12,r12,SystemCall_common@l
+ oris r12,r12,system_call_common@h
+ ori r12,r12,system_call_common@l
mtspr SRR0,r12
ori r10,r10,MSR_IR|MSR_DR|MSR_RI
mfspr r12,SRR1
rfid
b . /* prevent speculative execution */
- STD_EXCEPTION_PSERIES(0xd00, SingleStep)
- STD_EXCEPTION_PSERIES(0xe00, Trap_0e)
+ STD_EXCEPTION_PSERIES(0xd00, single_step)
+ STD_EXCEPTION_PSERIES(0xe00, trap_0e)
/* We need to deal with the Altivec unavailable exception
* here which is at 0xf20, thus in the middle of the
* trickery is thus necessary
*/
. = 0xf00
- b PerformanceMonitor_Pseries
+ b performance_monitor_pSeries
- STD_EXCEPTION_PSERIES(0xf20, AltivecUnavailable)
+ STD_EXCEPTION_PSERIES(0xf20, altivec_unavailable)
- STD_EXCEPTION_PSERIES(0x1300, InstructionBreakpoint)
- STD_EXCEPTION_PSERIES(0x1700, AltivecAssist)
+ STD_EXCEPTION_PSERIES(0x1300, instruction_breakpoint)
+ STD_EXCEPTION_PSERIES(0x1700, altivec_assist)
/* moved from 0xf00 */
- STD_EXCEPTION_PSERIES(0x3000, PerformanceMonitor)
+ STD_EXCEPTION_PSERIES(0x3000, performance_monitor)
. = 0x3100
-_GLOBAL(do_stab_bolted_Pseries)
+_GLOBAL(do_stab_bolted_pSeries)
mtcrf 0x80,r12
mfspr r12,SPRG2
EXCEPTION_PROLOG_PSERIES(PACA_EXSLB, .do_stab_bolted)
*/
. = NACA_PHYS_ADDR
.globl __end_interrupts
- .globl __start_naca
__end_interrupts:
-__start_naca:
#ifdef CONFIG_PPC_ISERIES
+ .globl naca
+naca:
.llong itVpdAreas
-#else
- .llong 0x0
#endif
- .llong 0x0
- .llong 0x0
- .llong paca
. = SYSTEMCFG_PHYS_ADDR
- .globl __end_naca
.globl __start_systemcfg
-__end_naca:
__start_systemcfg:
. = (SYSTEMCFG_PHYS_ADDR + PAGE_SIZE)
.globl __end_systemcfg
/*** ISeries-LPAR interrupt handlers ***/
- STD_EXCEPTION_ISERIES(0x200, MachineCheck, PACA_EXMC)
+ STD_EXCEPTION_ISERIES(0x200, machine_check, PACA_EXMC)
- .globl DataAccess_Iseries
-DataAccess_Iseries:
+ .globl data_access_iSeries
+data_access_iSeries:
mtspr SPRG1,r13
BEGIN_FTR_SECTION
mtspr SPRG2,r12
rlwimi r13,r12,16,0x20
mfcr r12
cmpwi r13,0x2c
- beq .do_stab_bolted_Iseries
+ beq .do_stab_bolted_iSeries
mtcrf 0x80,r12
mfspr r12,SPRG2
END_FTR_SECTION_IFCLR(CPU_FTR_SLB)
EXCEPTION_PROLOG_ISERIES_1(PACA_EXGEN)
EXCEPTION_PROLOG_ISERIES_2
- b DataAccess_common
+ b data_access_common
-.do_stab_bolted_Iseries:
+.do_stab_bolted_iSeries:
mtcrf 0x80,r12
mfspr r12,SPRG2
EXCEPTION_PROLOG_ISERIES_1(PACA_EXSLB)
EXCEPTION_PROLOG_ISERIES_2
b .do_stab_bolted
- .globl DataAccessSLB_Iseries
-DataAccessSLB_Iseries:
+ .globl data_access_slb_iSeries
+data_access_slb_iSeries:
mtspr SPRG1,r13 /* save r13 */
EXCEPTION_PROLOG_ISERIES_1(PACA_EXSLB)
std r3,PACA_EXSLB+EX_R3(r13)
mfspr r3,DAR
b .do_slb_miss
- STD_EXCEPTION_ISERIES(0x400, InstructionAccess, PACA_EXGEN)
+ STD_EXCEPTION_ISERIES(0x400, instruction_access, PACA_EXGEN)
- .globl InstructionAccessSLB_Iseries
-InstructionAccessSLB_Iseries:
+ .globl instruction_access_slb_iSeries
+instruction_access_slb_iSeries:
mtspr SPRG1,r13 /* save r13 */
EXCEPTION_PROLOG_ISERIES_1(PACA_EXSLB)
std r3,PACA_EXSLB+EX_R3(r13)
ld r3,PACALPPACA+LPPACASRR0(r13)
b .do_slb_miss
- MASKABLE_EXCEPTION_ISERIES(0x500, HardwareInterrupt)
- STD_EXCEPTION_ISERIES(0x600, Alignment, PACA_EXGEN)
- STD_EXCEPTION_ISERIES(0x700, ProgramCheck, PACA_EXGEN)
- STD_EXCEPTION_ISERIES(0x800, FPUnavailable, PACA_EXGEN)
- MASKABLE_EXCEPTION_ISERIES(0x900, Decrementer)
- STD_EXCEPTION_ISERIES(0xa00, Trap_0a, PACA_EXGEN)
- STD_EXCEPTION_ISERIES(0xb00, Trap_0b, PACA_EXGEN)
+ MASKABLE_EXCEPTION_ISERIES(0x500, hardware_interrupt)
+ STD_EXCEPTION_ISERIES(0x600, alignment, PACA_EXGEN)
+ STD_EXCEPTION_ISERIES(0x700, program_check, PACA_EXGEN)
+ STD_EXCEPTION_ISERIES(0x800, fp_unavailable, PACA_EXGEN)
+ MASKABLE_EXCEPTION_ISERIES(0x900, decrementer)
+ STD_EXCEPTION_ISERIES(0xa00, trap_0a, PACA_EXGEN)
+ STD_EXCEPTION_ISERIES(0xb00, trap_0b, PACA_EXGEN)
- .globl SystemCall_Iseries
-SystemCall_Iseries:
+ .globl system_call_iSeries
+system_call_iSeries:
mr r9,r13
mfspr r13,SPRG3
EXCEPTION_PROLOG_ISERIES_2
- b SystemCall_common
+ b system_call_common
- STD_EXCEPTION_ISERIES( 0xd00, SingleStep, PACA_EXGEN)
- STD_EXCEPTION_ISERIES( 0xe00, Trap_0e, PACA_EXGEN)
- STD_EXCEPTION_ISERIES( 0xf00, PerformanceMonitor, PACA_EXGEN)
+ STD_EXCEPTION_ISERIES( 0xd00, single_step, PACA_EXGEN)
+ STD_EXCEPTION_ISERIES( 0xe00, trap_0e, PACA_EXGEN)
+ STD_EXCEPTION_ISERIES( 0xf00, performance_monitor, PACA_EXGEN)
- .globl SystemReset_Iseries
-SystemReset_Iseries:
+ .globl system_reset_iSeries
+system_reset_iSeries:
mfspr r13,SPRG3 /* Get paca address */
mfmsr r24
ori r24,r24,MSR_RI
subi r1,r1,STACK_FRAME_OVERHEAD
cmpwi 0,r23,0
- beq iseries_secondary_smp_loop /* Loop until told to go */
+ beq iSeries_secondary_smp_loop /* Loop until told to go */
#ifdef SECONDARY_PROCESSORS
bne .__secondary_start /* Loop until told to go */
#endif
-iseries_secondary_smp_loop:
+iSeries_secondary_smp_loop:
/* Let the Hypervisor know we are alive */
/* 8002 is a call to HvCallCfg::getLps, a harmless Hypervisor function */
lis r3,0x8002
b 1b /* If SMP not configured, secondaries
* loop forever */
- .globl Decrementer_Iseries_masked
-Decrementer_Iseries_masked:
+ .globl decrementer_iSeries_masked
+decrementer_iSeries_masked:
li r11,1
stb r11,PACALPPACA+LPPACADECRINT(r13)
lwz r12,PACADEFAULTDECR(r13)
mtspr SPRN_DEC,r12
/* fall through */
- .globl HardwareInterrupt_Iseries_masked
-HardwareInterrupt_Iseries_masked:
+ .globl hardware_interrupt_iSeries_masked
+hardware_interrupt_iSeries_masked:
mtcrf 0x80,r9 /* Restore regs */
ld r11,PACALPPACA+LPPACASRR0(r13)
ld r12,PACALPPACA+LPPACASRR1(r13)
* Vectors for the FWNMI option. Share common code.
*/
. = 0x8000
- .globl SystemReset_FWNMI
-SystemReset_FWNMI:
+ .globl system_reset_fwnmi
+system_reset_fwnmi:
HMT_MEDIUM
mtspr SPRG1,r13 /* save r13 */
- EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, SystemReset_common)
- .globl MachineCheck_FWNMI
-MachineCheck_FWNMI:
+ EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, system_reset_common)
+ .globl machine_check_fwnmi
+machine_check_fwnmi:
HMT_MEDIUM
mtspr SPRG1,r13 /* save r13 */
- EXCEPTION_PROLOG_PSERIES(PACA_EXMC, MachineCheck_common)
+ EXCEPTION_PROLOG_PSERIES(PACA_EXMC, machine_check_common)
/*
* Space for the initial segment table
/*** Common interrupt handlers ***/
- STD_EXCEPTION_COMMON(0x100, SystemReset, .SystemResetException)
+ STD_EXCEPTION_COMMON(0x100, system_reset, .system_reset_exception)
/*
* Machine check is different because we use a different
* save area: PACA_EXMC instead of PACA_EXGEN.
*/
.align 7
- .globl MachineCheck_common
-MachineCheck_common:
+ .globl machine_check_common
+machine_check_common:
EXCEPTION_PROLOG_COMMON(0x200, PACA_EXMC)
DISABLE_INTS
bl .save_nvgprs
addi r3,r1,STACK_FRAME_OVERHEAD
- bl .MachineCheckException
+ bl .machine_check_exception
b .ret_from_except
- STD_EXCEPTION_COMMON_LITE(0x900, Decrementer, .timer_interrupt)
- STD_EXCEPTION_COMMON(0xa00, Trap_0a, .UnknownException)
- STD_EXCEPTION_COMMON(0xb00, Trap_0b, .UnknownException)
- STD_EXCEPTION_COMMON(0xd00, SingleStep, .SingleStepException)
- STD_EXCEPTION_COMMON(0xe00, Trap_0e, .UnknownException)
- STD_EXCEPTION_COMMON(0xf00, PerformanceMonitor, .PerformanceMonitorException)
- STD_EXCEPTION_COMMON(0x1300, InstructionBreakpoint, .InstructionBreakpointException)
+ STD_EXCEPTION_COMMON_LITE(0x900, decrementer, .timer_interrupt)
+ STD_EXCEPTION_COMMON(0xa00, trap_0a, .unknown_exception)
+ STD_EXCEPTION_COMMON(0xb00, trap_0b, .unknown_exception)
+ STD_EXCEPTION_COMMON(0xd00, single_step, .single_step_exception)
+ STD_EXCEPTION_COMMON(0xe00, trap_0e, .unknown_exception)
+ STD_EXCEPTION_COMMON(0xf00, performance_monitor, .performance_monitor_exception)
+ STD_EXCEPTION_COMMON(0x1300, instruction_breakpoint, .instruction_breakpoint_exception)
#ifdef CONFIG_ALTIVEC
- STD_EXCEPTION_COMMON(0x1700, AltivecAssist, .AltivecAssistException)
+ STD_EXCEPTION_COMMON(0x1700, altivec_assist, .altivec_assist_exception)
#else
- STD_EXCEPTION_COMMON(0x1700, AltivecAssist, .UnknownException)
+ STD_EXCEPTION_COMMON(0x1700, altivec_assist, .unknown_exception)
#endif
/*
* r9 - r13 are saved in paca->exgen.
*/
.align 7
- .globl DataAccess_common
-DataAccess_common:
+ .globl data_access_common
+data_access_common:
mfspr r10,DAR
std r10,PACA_EXGEN+EX_DAR(r13)
mfspr r10,DSISR
b .do_hash_page /* Try to handle as hpte fault */
.align 7
- .globl InstructionAccess_common
-InstructionAccess_common:
+ .globl instruction_access_common
+instruction_access_common:
EXCEPTION_PROLOG_COMMON(0x400, PACA_EXGEN)
ld r3,_NIP(r1)
andis. r4,r12,0x5820
b .do_hash_page /* Try to handle as hpte fault */
.align 7
- .globl HardwareInterrupt_common
- .globl HardwareInterrupt_entry
-HardwareInterrupt_common:
+ .globl hardware_interrupt_common
+ .globl hardware_interrupt_entry
+hardware_interrupt_common:
EXCEPTION_PROLOG_COMMON(0x500, PACA_EXGEN)
-HardwareInterrupt_entry:
+hardware_interrupt_entry:
DISABLE_INTS
addi r3,r1,STACK_FRAME_OVERHEAD
bl .do_IRQ
b .ret_from_except_lite
.align 7
- .globl Alignment_common
-Alignment_common:
+ .globl alignment_common
+alignment_common:
mfspr r10,DAR
std r10,PACA_EXGEN+EX_DAR(r13)
mfspr r10,DSISR
bl .save_nvgprs
addi r3,r1,STACK_FRAME_OVERHEAD
ENABLE_INTS
- bl .AlignmentException
+ bl .alignment_exception
b .ret_from_except
.align 7
- .globl ProgramCheck_common
-ProgramCheck_common:
+ .globl program_check_common
+program_check_common:
EXCEPTION_PROLOG_COMMON(0x700, PACA_EXGEN)
bl .save_nvgprs
addi r3,r1,STACK_FRAME_OVERHEAD
ENABLE_INTS
- bl .ProgramCheckException
+ bl .program_check_exception
b .ret_from_except
.align 7
- .globl FPUnavailable_common
-FPUnavailable_common:
+ .globl fp_unavailable_common
+fp_unavailable_common:
EXCEPTION_PROLOG_COMMON(0x800, PACA_EXGEN)
bne .load_up_fpu /* if from user, just load it up */
bl .save_nvgprs
addi r3,r1,STACK_FRAME_OVERHEAD
ENABLE_INTS
- bl .KernelFPUnavailableException
+ bl .kernel_fp_unavailable_exception
BUG_OPCODE
.align 7
- .globl AltivecUnavailable_common
-AltivecUnavailable_common:
+ .globl altivec_unavailable_common
+altivec_unavailable_common:
EXCEPTION_PROLOG_COMMON(0xf20, PACA_EXGEN)
#ifdef CONFIG_ALTIVEC
bne .load_up_altivec /* if from user, just load it up */
bl .save_nvgprs
addi r3,r1,STACK_FRAME_OVERHEAD
ENABLE_INTS
- bl .AltivecUnavailableException
+ bl .altivec_unavailable_exception
b .ret_from_except
/*
/*
* On pSeries, secondary processors spin in the following code.
- * At entry, r3 = this processor's number (in Linux terms, not hardware).
+ * At entry, r3 = this processor's number (physical cpu id)
*/
-_GLOBAL(pseries_secondary_smp_init)
+_GLOBAL(pSeries_secondary_smp_init)
+ mr r24,r3
+
/* turn on 64-bit mode */
bl .enable_64b_mode
isync
- /* Set up a paca value for this processor. */
- LOADADDR(r24, paca) /* Get base vaddr of paca array */
- mulli r13,r3,PACA_SIZE /* Calculate vaddr of right paca */
- add r13,r13,r24 /* for this processor. */
-
- mtspr SPRG3,r13 /* Save vaddr of paca in SPRG3 */
- mr r24,r3 /* __secondary_start needs cpu# */
+ /* Copy some CPU settings from CPU 0 */
+ bl .__restore_cpu_setup
-1:
- HMT_LOW
+ /* Set up a paca value for this processor. Since we have the
+ * physical cpu id in r3, we need to search the pacas to find
+ * which logical id maps to our physical one.
+ */
+ LOADADDR(r13, paca) /* Get base vaddr of paca array */
+ li r5,0 /* logical cpu id */
+1: lhz r6,PACAHWCPUID(r13) /* Load HW procid from paca */
+ cmpw r6,r24 /* Compare to our id */
+ beq 2f
+ addi r13,r13,PACA_SIZE /* Loop to next PACA on miss */
+ addi r5,r5,1
+ cmpwi r5,NR_CPUS
+ blt 1b
+
+99: HMT_LOW /* Couldn't find our CPU id */
+ b 99b
+
+2: mtspr SPRG3,r13 /* Save vaddr of paca in SPRG3 */
+ /* From now on, r24 is expected to be logica cpuid */
+ mr r24,r5
+3: HMT_LOW
lbz r23,PACAPROCSTART(r13) /* Test if this processor should */
/* start. */
sync
bne .__secondary_start
#endif
#endif
- b 1b /* Loop until told to go */
+ b 3b /* Loop until told to go */
+
#ifdef CONFIG_PPC_ISERIES
_STATIC(__start_initialization_iSeries)
/* Clear out the BSS */
SET_REG_TO_CONST(r4, SYSTEMCFG_VIRT_ADDR)
std r4,0(r9) /* set the systemcfg pointer */
- LOADADDR(r9,naca)
- SET_REG_TO_CONST(r4, NACA_VIRT_ADDR)
- std r4,0(r9) /* set the naca pointer */
-
- /* Get the pointer to the segment table */
- ld r6,PACA(r4) /* Get the base paca pointer */
- ld r4,PACASTABVIRT(r6)
-
bl .iSeries_early_setup
/* relocation is on at this point */
li r27,SYSTEMCFG_PHYS_ADDR
std r27,0(r6) /* set the value of systemcfg */
- /* setup the naca pointer which is needed by *tab_initialize */
- LOADADDR(r6,naca)
- sub r6,r6,r26 /* addr of the variable naca */
- li r27,NACA_PHYS_ADDR
- std r27,0(r6) /* set the value of naca */
-
#ifdef CONFIG_HMT
/* Start up the second thread on cpu 0 */
mfspr r3,PVR
91:
#endif
-#ifdef CONFIG_SMP
- /* All secondary cpus are now spinning on a common
- * spinloop, release them all now so they can start
- * to spin on their individual paca spinloops.
- * For non SMP kernels, the secondary cpus never
- * get out of the common spinloop.
- */
- li r3,1
- LOADADDR(r5,__secondary_hold_spinloop)
- tophys(r4,r5)
- std r3,0(r4)
-#endif
-
/* The following gets the stack and TOC set up with the regs */
/* pointing to the real addr of the kernel stack. This is */
/* all done to support the C function call below which sets */
li r0,0
stdu r0,-STACK_FRAME_OVERHEAD(r1)
- /* set up the TOC (physical address) */
+ /* set up the TOC (physical address) */
LOADADDR(r2,__toc_start)
addi r2,r2,0x4000
addi r2,r2,0x4000
mr r5,r26
bl .identify_cpu
+ /* Save some low level config HIDs of CPU0 to be copied to
+ * other CPUs later on, or used for suspend/resume
+ */
+ bl .__save_cpu_setup
+ sync
+
/* Setup a valid physical PACA pointer in SPRG3 for early_setup
* note that boot_cpuid can always be 0 nowadays since there is
* nowhere it can be initialized differently before we reach this
SET_REG_TO_CONST(r8, SYSTEMCFG_VIRT_ADDR)
std r8,0(r9)
- /* setup the naca pointer */
- LOADADDR(r9,naca)
- SET_REG_TO_CONST(r8, NACA_VIRT_ADDR)
- std r8,0(r9) /* set the value of the naca ptr */
-
LOADADDR(r26, boot_cpuid)
lwz r26,0(r26)
101:
#endif
mr r3,r24
- b .pseries_secondary_smp_init
+ b .pSeries_secondary_smp_init
#ifdef CONFIG_HMT
_GLOBAL(hmt_start_secondary)
blr
#endif
+#if defined(CONFIG_SMP) && !defined(CONFIG_PPC_ISERIES)
+_GLOBAL(smp_release_cpus)
+ /* All secondary cpus are spinning on a common
+ * spinloop, release them all now so they can start
+ * to spin on their individual paca spinloops.
+ * For non SMP kernels, the secondary cpus never
+ * get out of the common spinloop.
+ */
+ li r3,1
+ LOADADDR(r5,__secondary_hold_spinloop)
+ std r3,0(r5)
+ sync
+ blr
+#endif /* CONFIG_SMP && !CONFIG_PPC_ISERIES */
+
+
/*
* We put a few things here that have to be page-aligned.
* This stuff goes at the beginning of the data segment,
ioremap_dir:
.space 4096
+#ifdef CONFIG_SMP
/* 1 page segment table per cpu (max 48, cpu0 allocated at STAB0_PHYS_ADDR) */
.globl stab_array
stab_array:
.space 4096 * 48
+#endif
/*
* This space gets a copy of optional info passed to us by the bootstrap
git://git.onelab.eu / linux-2.6.git / blobdiff