VServer 1.9.2 (patch-2.6.8.1-vs1.9.2.diff)

[linux-2.6.git] / arch / sh / kernel / cpu / init.c

diff --git a/arch/sh/kernel/cpu/init.c b/arch/sh/kernel/cpu/init.c
index a81b340..975103f 100644 (file)
--- a/arch/sh/kernel/cpu/init.c
+++ b/arch/sh/kernel/cpu/init.c
@@ -42,7 +42,7 @@ onchip_setup(dsp);
  */
 static void __init cache_init(void)
 {
-       unsigned long ccr, flags = 0;
+       unsigned long ccr, flags;
 
        if (cpu_data->type == CPU_SH_NONE)
                panic("Unknown CPU");
@@ -54,42 +54,50 @@ static void __init cache_init(void)
         * If the cache is already enabled .. flush it.
         */
        if (ccr & CCR_CACHE_ENABLE) {
-               unsigned long entries, i, j;
+               unsigned long ways, waysize, addrstart;
 
-               entries = cpu_data->dcache.sets;
+               waysize = cpu_data->dcache.sets;
 
                /*
                 * If the OC is already in RAM mode, we only have
                 * half of the entries to flush..
                 */
                if (ccr & CCR_CACHE_ORA)
-                       entries >>= 1;
+                       waysize >>= 1;
 
-               for (i = 0; i < entries; i++) {
-                       for (j = 0; j < cpu_data->dcache.ways; j++) {
-                               unsigned long data, addr;
+               waysize <<= cpu_data->dcache.entry_shift;
 
-                               addr = CACHE_OC_ADDRESS_ARRAY |
-                                       (j << cpu_data->dcache.way_shift) |
-                                       (i << cpu_data->dcache.entry_shift);
+#ifdef CCR_CACHE_EMODE
+               /* If EMODE is not set, we only have 1 way to flush. */
+               if (!(ccr & CCR_CACHE_EMODE))
+                       ways = 1;
+               else
+#endif
+                       ways = cpu_data->dcache.ways;
 
-                               data = ctrl_inl(addr);
+               addrstart = CACHE_OC_ADDRESS_ARRAY;
+               do {
+                       unsigned long addr;
 
-                               if ((data & (SH_CACHE_UPDATED | SH_CACHE_VALID))
-                                       == (SH_CACHE_UPDATED | SH_CACHE_VALID))
-                                       ctrl_outl(data & ~SH_CACHE_UPDATED, addr);
-                       }
-               }
+                       for (addr = addrstart;
+                            addr < addrstart + waysize;
+                            addr += cpu_data->dcache.linesz)
+                               ctrl_outl(0, addr);
+
+                       addrstart += cpu_data->dcache.way_incr;
+               } while (--ways);
        }
 
        /* 
         * Default CCR values .. enable the caches
-        * and flush them immediately..
+        * and invalidate them immediately..
         */
-       flags |= CCR_CACHE_ENABLE | CCR_CACHE_INVALIDATE;
-       
+       flags = CCR_CACHE_ENABLE | CCR_CACHE_INVALIDATE;
+
 #ifdef CCR_CACHE_EMODE
-       flags |= (ccr & CCR_CACHE_EMODE);
+       /* Force EMODE if possible */
+       if (cpu_data->dcache.ways > 1)
+               flags |= CCR_CACHE_EMODE;
 #endif
 
 #ifdef CONFIG_SH_WRITETHROUGH
@@ -145,8 +153,8 @@ static void __init dsp_init(void)
 
        /* If the DSP bit is still set, this CPU has a DSP */
        if (sr & SR_DSP)
-               set_bit(CPU_HAS_DSP, &(cpu_data->flags));
-       
+               cpu_data->flags |= CPU_HAS_DSP;
+
        /* Now that we've determined the DSP status, clear the DSP bit. */
        release_dsp();
 }
@@ -184,7 +192,7 @@ asmlinkage void __init sh_cpu_init(void)
        }
 
        /* FPU initialization */
-       if (test_bit(CPU_HAS_FPU, &(cpu_data->flags))) {
+       if ((cpu_data->flags & CPU_HAS_FPU)) {
                clear_thread_flag(TIF_USEDFPU);
                current->used_math = 0;
        }