fedora core 6 1.2949 + vserver 2.2.0

[linux-2.6.git] / arch / sh / kernel / head.S

diff --git a/arch/sh/kernel/head.S b/arch/sh/kernel/head.S
index 9b9e6ef..71a3ad7 100644 (file)
--- a/arch/sh/kernel/head.S
+++ b/arch/sh/kernel/head.S
@@ -11,6 +11,18 @@
  * Head.S contains the SH exception handlers and startup code.
  */
 #include <linux/linkage.h>
+#include <asm/thread_info.h>
+
+#ifdef CONFIG_CPU_SH4A
+#define SYNCO()                synco
+
+#define PREFI(label, reg)      \
+       mov.l   label, reg;     \
+       prefi   @reg
+#else
+#define SYNCO()
+#define PREFI(label, reg)
+#endif
 
        .section        .empty_zero_page, "aw"
 ENTRY(empty_zero_page)
@@ -21,7 +33,8 @@ ENTRY(empty_zero_page)
        .long   0x00360000      /* INITRD_START */
        .long   0x000a0000      /* INITRD_SIZE */
        .long   0
-       .balign 4096,0,4096
+1:
+       .skip   PAGE_SIZE - empty_zero_page - 1b
 
        .text   
 /*
@@ -41,19 +54,31 @@ ENTRY(_stext)
        ldc     r0, sr
        !                       Initialize global interrupt mask
        mov     #0, r0
+#ifdef CONFIG_CPU_HAS_SR_RB
        ldc     r0, r6_bank
+#endif
+       
+       /*
+        * Prefetch if possible to reduce cache miss penalty.
+        *
+        * We do this early on for SH-4A as a micro-optimization,
+        * as later on we will have speculative execution enabled
+        * and this will become less of an issue.
+        */
+       PREFI(5f, r0)
+       PREFI(6f, r0)
+
        !
        mov.l   2f, r0
        mov     r0, r15         ! Set initial r15 (stack pointer)
-       mov     #0x20, r1       !
-       shll8   r1              ! r1 = 8192
+       mov     #(THREAD_SIZE >> 10), r1
+       shll8   r1              ! r1 = THREAD_SIZE
+       shll2   r1
        sub     r1, r0          !
+#ifdef CONFIG_CPU_HAS_SR_RB
        ldc     r0, r7_bank     ! ... and initial thread_info
-       !
-       !                       Additional CPU initialization
-       mov.l   6f, r0
-       jsr     @r0
-        nop
+#endif
+       
        !                       Clear BSS area
        mov.l   3f, r1
        add     #4, r1
@@ -62,14 +87,26 @@ ENTRY(_stext)
 9:     cmp/hs  r2, r1
        bf/s    9b              ! while (r1 < r2)
         mov.l  r0,@-r2
+
+       !                       Additional CPU initialization
+       mov.l   6f, r0
+       jsr     @r0
+        nop
+
+       SYNCO()                 ! Wait for pending instructions..
+
        !                       Start kernel
        mov.l   5f, r0
        jmp     @r0
         nop
 
        .balign 4
+#if defined(CONFIG_CPU_SH2)
+1:     .long   0x000000F0              ! IMASK=0xF
+#else
 1:     .long   0x400080F0              ! MD=1, RB=0, BL=0, FD=1, IMASK=0xF
-2:     .long   stack
+#endif
+2:     .long   init_thread_union+THREAD_SIZE
 3:     .long   __bss_start
 4:     .long   _end
 5:     .long   start_kernel