vserver 1.9.5.x5

[linux-2.6.git] / arch / sh / mm / cache-sh4.c

diff --git a/arch/sh/mm/cache-sh4.c b/arch/sh/mm/cache-sh4.c
index adb99d8..a877087 100644 (file)
--- a/arch/sh/mm/cache-sh4.c
+++ b/arch/sh/mm/cache-sh4.c
@@ -1,10 +1,13 @@
-/* $Id: cache-sh4.c,v 1.26 2004/02/19 12:47:24 lethal Exp $
- *
- *  linux/arch/sh/mm/cache-sh4.c
+/*
+ * arch/sh/mm/cache-sh4.c
  *
  * Copyright (C) 1999, 2000, 2002  Niibe Yutaka
  * Copyright (C) 2001, 2002, 2003, 2004  Paul Mundt
  * Copyright (C) 2003  Richard Curnow
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
  */
 
 #include <linux/config.h>
@@ -28,126 +31,6 @@ static void __flush_cache_4096_all_ex(unsigned long start);
 extern void __flush_dcache_all(void);
 static void __flush_dcache_all_ex(void);
 
-int __init detect_cpu_and_cache_system(void)
-{
-       unsigned long pvr, prr, cvr;
-       unsigned long size;
-
-       static unsigned long sizes[16] = {
-               [1] = (1 << 12),
-               [2] = (1 << 13),
-               [4] = (1 << 14),
-               [8] = (1 << 15),
-               [9] = (1 << 16)
-       };
-
-       pvr = (ctrl_inl(CCN_PVR) >> 8) & 0xffff;
-       prr = (ctrl_inl(CCN_PRR) >> 4) & 0xff;
-       cvr = (ctrl_inl(CCN_CVR));
-
-       /*
-        * Setup some sane SH-4 defaults for the icache
-        */
-       cpu_data->icache.way_incr       = (1 << 13);
-       cpu_data->icache.entry_shift    = 5;
-       cpu_data->icache.entry_mask     = 0x1fe0;
-       cpu_data->icache.sets           = 256;
-       cpu_data->icache.ways           = 1;
-       cpu_data->icache.linesz         = L1_CACHE_BYTES;
-
-       /*
-        * And again for the dcache ..
-        */
-       cpu_data->dcache.way_incr       = (1 << 14);
-       cpu_data->dcache.entry_shift    = 5;
-       cpu_data->dcache.entry_mask     = 0x3fe0;
-       cpu_data->dcache.sets           = 512;
-       cpu_data->dcache.ways           = 1;
-       cpu_data->dcache.linesz         = L1_CACHE_BYTES;
-
-       /* Set the FPU flag, virtually all SH-4's have one */
-       cpu_data->flags |= CPU_HAS_FPU;
-
-       /*
-        * Probe the underlying processor version/revision and
-        * adjust cpu_data setup accordingly.
-        */
-       switch (pvr) {
-       case 0x205:
-               cpu_data->type = CPU_SH7750;
-               cpu_data->flags |= CPU_HAS_P2_FLUSH_BUG;
-               break;
-       case 0x206:
-               cpu_data->type = CPU_SH7750S;
-
-               /* 
-                * FIXME: This is needed for 7750, but do we need it for the
-                * 7750S too? For now, assume we do.. -- PFM
-                */
-               cpu_data->flags |= CPU_HAS_P2_FLUSH_BUG;
-
-               break;
-       case 0x1100:
-               cpu_data->type = CPU_SH7751;
-               break;
-       case 0x8000:
-               cpu_data->type = CPU_ST40RA;
-               break;
-       case 0x8100:
-               cpu_data->type = CPU_ST40GX1;
-               break;
-       case 0x700:
-               cpu_data->type = CPU_SH4_501;
-               cpu_data->icache.ways = 2;
-               cpu_data->dcache.ways = 2;
-
-               /* No FPU on the SH4-500 series.. */
-               cpu_data->flags &= ~CPU_HAS_FPU;
-               break;
-       case 0x600:
-               cpu_data->type = CPU_SH4_202;
-               cpu_data->icache.ways = 2;
-               cpu_data->dcache.ways = 2;
-               break;
-       case 0x500 ... 0x501:
-               switch (prr) {
-                   case 0x10: cpu_data->type = CPU_SH7750R; break;
-                   case 0x11: cpu_data->type = CPU_SH7751R; break;
-                   case 0x50: cpu_data->type = CPU_SH7760;  break;
-               }
-
-               cpu_data->icache.ways = 2;
-               cpu_data->dcache.ways = 2;
-
-               break;
-       default:
-               cpu_data->type = CPU_SH_NONE;
-               break;
-       }
-
-       /*
-        * On anything that's not a direct-mapped cache, look to the CVR
-        * for I/D-cache specifics.
-        */
-       if (cpu_data->icache.ways > 1) {
-               size = sizes[(cvr >> 20) & 0xf];
-               cpu_data->icache.way_incr       = size / cpu_data->icache.ways;
-               cpu_data->icache.sets           = (size >> 6);
-               cpu_data->icache.entry_mask     =
-                       ((size / cpu_data->icache.ways) - (1 << 5));
-       }
-
-       if (cpu_data->dcache.ways > 1) {
-               size = sizes[(cvr >> 16) & 0xf];
-               cpu_data->dcache.way_incr       = size / cpu_data->dcache.ways;
-               cpu_data->dcache.sets           = (size >> 6);
-               cpu_data->dcache.entry_mask     =
-                       ((size / cpu_data->dcache.ways) - (1 << 5));
-       }
-
-       return 0;
-}
-
 /*
  * SH-4 has virtually indexed and physically tagged cache.
  */