linux 2.6.16.38 w/ vs2.0.3-rc1

[linux-2.6.git] / arch / sparc64 / kernel / itlb_base.S

diff --git a/arch/sparc64/kernel/itlb_base.S b/arch/sparc64/kernel/itlb_base.S
index b5e32df..4951ff8 100644 (file)
--- a/arch/sparc64/kernel/itlb_base.S
+++ b/arch/sparc64/kernel/itlb_base.S
@@ -15,14 +15,12 @@
  */
 #define CREATE_VPTE_OFFSET1(r1, r2) \
                                srax    r1, 10, r2
-#define CREATE_VPTE_OFFSET2(r1, r2)
-#define CREATE_VPTE_NOP                nop
+#define CREATE_VPTE_OFFSET2(r1, r2) nop
 #else /* PAGE_SHIFT */
 #define CREATE_VPTE_OFFSET1(r1, r2) \
                                srax    r1, PAGE_SHIFT, r2
 #define CREATE_VPTE_OFFSET2(r1, r2) \
                                sllx    r2, 3, r2
-#define CREATE_VPTE_NOP
 #endif /* PAGE_SHIFT */
 
 
@@ -36,6 +34,7 @@
  */
 
 /* ITLB ** ICACHE line 1: Quick user TLB misses                */
+       mov             TLB_SFSR, %g1
        ldxa            [%g1 + %g1] ASI_IMMU, %g4       ! Get TAG_ACCESS
        CREATE_VPTE_OFFSET1(%g4, %g6)                   ! Create VPTE offset
        CREATE_VPTE_OFFSET2(%g4, %g6)                   ! Create VPTE offset
@@ -43,41 +42,38 @@
 1:     brgez,pn        %g5, 3f                         ! Not valid, branch out
         sethi          %hi(_PAGE_EXEC), %g4            ! Delay-slot
        andcc           %g5, %g4, %g0                   ! Executable?
+
+/* ITLB ** ICACHE line 2: Real faults                  */
        be,pn           %xcc, 3f                        ! Nope, branch.
         nop                                            ! Delay-slot
 2:     stxa            %g5, [%g0] ASI_ITLB_DATA_IN     ! Load PTE into TLB
        retry                                           ! Trap return
-3:     rdpr            %pstate, %g4                    ! Move into alternate globals
-
-/* ITLB ** ICACHE line 2: Real faults                  */
+3:     rdpr            %pstate, %g4                    ! Move into alt-globals
        wrpr            %g4, PSTATE_AG|PSTATE_MG, %pstate
        rdpr            %tpc, %g5                       ! And load faulting VA
        mov             FAULT_CODE_ITLB, %g4            ! It was read from ITLB
-sparc64_realfault_common:                              ! Called by TL0 dtlb_miss too
+
+/* ITLB ** ICACHE line 3: Finish faults        */
+sparc64_realfault_common:                              ! Called by dtlb_miss
        stb             %g4, [%g6 + TI_FAULT_CODE]
        stx             %g5, [%g6 + TI_FAULT_ADDR]
        ba,pt           %xcc, etrap                     ! Save state
 1:      rd             %pc, %g7                        ! ...
-       nop
-
-/* ITLB ** ICACHE line 3: Finish faults + window fixups        */
        call            do_sparc64_fault                ! Call fault handler
         add            %sp, PTREGS_OFF, %o0! Compute pt_regs arg
        ba,pt           %xcc, rtrap_clr_l6              ! Restore cpu state
         nop
+
+/* ITLB ** ICACHE line 4: Window fixups */
 winfix_trampoline:
        rdpr            %tpc, %g3                       ! Prepare winfixup TNPC
-       or              %g3, 0x7c, %g3                  ! Compute offset to branch
+       or              %g3, 0x7c, %g3                  ! Compute branch offset
        wrpr            %g3, %tnpc                      ! Write it into TNPC
        done                                            ! Do it to it
-
-/* ITLB ** ICACHE line 4: Unused...    */
        nop
        nop
        nop
        nop
-       CREATE_VPTE_NOP
 
 #undef CREATE_VPTE_OFFSET1
 #undef CREATE_VPTE_OFFSET2
-#undef CREATE_VPTE_NOP