vserver 2.0 rc7

[linux-2.6.git] / arch / sparc64 / kernel / rtrap.S

diff --git a/arch/sparc64/kernel/rtrap.S b/arch/sparc64/kernel/rtrap.S
index b7c3277..0696ed4 100644 (file)
--- a/arch/sparc64/kernel/rtrap.S
+++ b/arch/sparc64/kernel/rtrap.S
@@ -223,7 +223,10 @@ rt_continue:       ldx                     [%sp + PTREGS_OFF + PT_V9_G1], %g1
                ldx                     [%sp + PTREGS_OFF + PT_V9_G3], %g3
                ldx                     [%sp + PTREGS_OFF + PT_V9_G4], %g4
                ldx                     [%sp + PTREGS_OFF + PT_V9_G5], %g5
-               ldx                     [%sp + PTREGS_OFF + PT_V9_G6], %g6
+               mov                     TSB_REG, %g6
+               brnz,a,pn               %l3, 1f
+                ldxa                   [%g6] ASI_IMMU, %g5
+1:             ldx                     [%sp + PTREGS_OFF + PT_V9_G6], %g6
                ldx                     [%sp + PTREGS_OFF + PT_V9_G7], %g7
                wrpr                    %g0, RTRAP_PSTATE_AG_IRQOFF, %pstate
                ldx                     [%sp + PTREGS_OFF + PT_V9_I0], %i0
@@ -250,6 +253,10 @@ rt_continue:       ldx                     [%sp + PTREGS_OFF + PT_V9_G1], %g1
                brnz,pn                 %l3, kern_rtt
                 mov                    PRIMARY_CONTEXT, %l7
                ldxa                    [%l7 + %l7] ASI_DMMU, %l0
+cplus_rtrap_insn_1:
+               sethi                   %hi(0), %l1
+               sllx                    %l1, 32, %l1
+               or                      %l0, %l1, %l0
                stxa                    %l0, [%l7] ASI_DMMU
                flush                   %g6
                rdpr                    %wstate, %l1
@@ -298,10 +305,10 @@ kern_fpucheck:    ldub                    [%g6 + TI_FPDEPTH], %l5
                andcc                   %l2, FPRS_FEF, %g0
                be,pn                   %icc, 5f
                 sll                    %o0, 3, %o5
-               rd                      %fprs, %g5
+               rd                      %fprs, %g1
 
-               wr                      %g5, FPRS_FEF, %fprs
-               ldx                     [%o1 + %o5], %g5
+               wr                      %g1, FPRS_FEF, %fprs
+               ldx                     [%o1 + %o5], %g1
                add                     %g6, TI_XFSR, %o1
                membar                  #StoreLoad | #LoadLoad
                sll                     %o0, 8, %o2
@@ -313,7 +320,7 @@ kern_fpucheck:      ldub                    [%g6 + TI_FPDEPTH], %l5
                ldda                    [%o4 + %o2] ASI_BLK_P, %f16
 1:             andcc                   %l2, FPRS_DU, %g0
                be,pn                   %icc, 1f
-                wr                     %g5, 0, %gsr
+                wr                     %g1, 0, %gsr
                add                     %o2, 0x80, %o2
                ldda                    [%o3 + %o2] ASI_BLK_P, %f32
                ldda                    [%o4 + %o2] ASI_BLK_P, %f48
@@ -335,3 +342,21 @@ kern_fpucheck:     ldub                    [%g6 + TI_FPDEPTH], %l5
                wr                      %g0, FPRS_DU, %fprs
                ba,pt                   %xcc, rt_continue
                 stb                    %l5, [%g6 + TI_FPDEPTH]
+
+cplus_rinsn_1:
+               sethi                   %uhi(CTX_CHEETAH_PLUS_NUC), %l1
+
+               .globl                  cheetah_plus_patch_rtrap
+cheetah_plus_patch_rtrap:
+               /* We configure the dTLB512_0 for 4MB pages and the
+                * dTLB512_1 for 8K pages when in context zero.
+                */
+               sethi                   %hi(cplus_rinsn_1), %o0
+               sethi                   %hi(cplus_rtrap_insn_1), %o2
+               lduw                    [%o0 + %lo(cplus_rinsn_1)], %o1
+               or                      %o2, %lo(cplus_rtrap_insn_1), %o2
+               stw                     %o1, [%o2]
+               flush                   %o2
+
+               retl
+                nop