vserver 1.9.3

[linux-2.6.git] / arch / sparc64 / lib / bitops.S

diff --git a/arch/sparc64/lib/bitops.S b/arch/sparc64/lib/bitops.S
index 0c2aacc..c1e3700 100644 (file)
--- a/arch/sparc64/lib/bitops.S
+++ b/arch/sparc64/lib/bitops.S
@@ -9,6 +9,7 @@
        .text
        .align  64
        .globl  ___test_and_set_bit
+       .type   ___test_and_set_bit,#function
 ___test_and_set_bit:   /* %o0=nr, %o1=addr */
        srlx    %o0, 6, %g1
        mov     1, %g5
@@ -26,8 +27,10 @@ ___test_and_set_bit: /* %o0=nr, %o1=addr */
         ldx    [%o1], %g7
 2:     retl
         membar #StoreLoad | #StoreStore
+       .size   ___test_and_set_bit, .-___test_and_set_bit
 
        .globl  ___test_and_clear_bit
+       .type   ___test_and_clear_bit,#function
 ___test_and_clear_bit: /* %o0=nr, %o1=addr */
        srlx    %o0, 6, %g1
        mov     1, %g5
@@ -45,8 +48,10 @@ ___test_and_clear_bit:       /* %o0=nr, %o1=addr */
         ldx    [%o1], %g7
 2:     retl
         membar #StoreLoad | #StoreStore
+       .size   ___test_and_clear_bit, .-___test_and_clear_bit
 
        .globl  ___test_and_change_bit
+       .type   ___test_and_change_bit,#function
 ___test_and_change_bit:        /* %o0=nr, %o1=addr */
        srlx    %o0, 6, %g1
        mov     1, %g5
@@ -64,41 +69,4 @@ ___test_and_change_bit:      /* %o0=nr, %o1=addr */
 2:     retl
         membar #StoreLoad | #StoreStore
        nop
-
-       .globl  ___test_and_set_le_bit
-___test_and_set_le_bit:        /* %o0=nr, %o1=addr */
-       srlx    %o0, 5, %g1
-       mov     1, %g5
-       sllx    %g1, 2, %g3
-       and     %o0, 31, %g2
-       sllx    %g5, %g2, %g5
-       add     %o1, %g3, %o1
-       lduwa   [%o1] ASI_PL, %g7
-1:     andcc   %g7, %g5, %o0
-       bne,pn  %icc, 2f
-        xor    %g7, %g5, %g1
-       casa    [%o1] ASI_PL, %g7, %g1
-       cmp     %g7, %g1
-       bne,a,pn %icc, 1b
-        lduwa  [%o1] ASI_PL, %g7
-2:     retl
-        membar #StoreLoad | #StoreStore
-
-       .globl  ___test_and_clear_le_bit
-___test_and_clear_le_bit:      /* %o0=nr, %o1=addr */
-       srlx    %o0, 5, %g1
-       mov     1, %g5
-       sllx    %g1, 2, %g3
-       and     %o0, 31, %g2
-       sllx    %g5, %g2, %g5
-       add     %o1, %g3, %o1
-       lduwa   [%o1] ASI_PL, %g7
-1:     andcc   %g7, %g5, %o0
-       be,pn   %icc, 2f
-        xor    %g7, %g5, %g1
-       casa    [%o1] ASI_PL, %g7, %g1
-       cmp     %g7, %g1
-       bne,a,pn %icc, 1b
-        lduwa  [%o1] ASI_PL, %g7
-2:     retl
-        membar #StoreLoad | #StoreStore
+       .size   ___test_and_change_bit, .-___test_and_change_bit