u8 reg59h = 0, reset = (hwif->channel) ? 0x80 : 0x40;
u8 regXXh = 0, state_reg= (hwif->channel) ? 0x57 : 0x53;
- if (!hwif)
- return -EINVAL;
-
// hwif->bus_state = state;
pci_read_config_byte(dev, 0x59, ®59h);
u8 tristate = 0, resetmask = 0, bus_reg = 0;
u16 tri_reg;
- if (!hwif)
- return -EINVAL;
-
hwif->bus_state = state;
if (hwif->channel) {
/* Unsupported */
} else if (pll == F_LOW_PCI_50) {
if (hpt_minimum_revision(dev,8))
- pci_set_drvdata(dev, NULL);
+ pci_set_drvdata(dev, (void *) fifty_base_hpt370a);
else if (hpt_minimum_revision(dev,5))
pci_set_drvdata(dev, (void *) fifty_base_hpt372);
else if (hpt_minimum_revision(dev,4))
if (pci_get_drvdata(dev))
goto init_hpt37X_done;
- if (hpt_minimum_revision(dev,8))
- {
- printk(KERN_ERR "HPT374: Only 33MHz PCI timings are supported.\n");
- return -EOPNOTSUPP;
- }
/*
* adjust PLL based upon PCI clock, enable it, and wait for
* stabilization.
MODULE_DEVICE_TABLE(pci, hpt366_pci_tbl);
static struct pci_driver driver = {
- .name = "HPT366 IDE",
+ .name = "HPT366_IDE",
.id_table = hpt366_pci_tbl,
.probe = hpt366_init_one,
};