* Released under terms of General Public License
*/
+#include <linux/config.h>
#include <linux/types.h>
#include <linux/module.h>
#include <linux/kernel.h>
#define MC1 0x02 /* DMA"C" timing */
#define MC0 0x01 /* DMA"C" timing */
+#if 0
+ unsigned long bibma = pci_resource_start(dev, 4);
+ u8 hi = 0, lo = 0;
+
+ u8 sc1c = inb_p((u16)bibma + 0x1c);
+ u8 sc1e = inb_p((u16)bibma + 0x1e);
+ u8 sc1f = inb_p((u16)bibma + 0x1f);
+
+ p += sprintf(p, "Host Mode : %s\n",
+ (sc1f & 0x08) ? "Tri-Stated" : "Normal");
+ p += sprintf(p, "Bus Clocking : %s\n",
+ ((sc1f & 0xC0) == 0xC0) ? "100 External" :
+ ((sc1f & 0x80) == 0x80) ? "66 External" :
+ ((sc1f & 0x40) == 0x40) ? "33 External" : "33 PCI Internal");
+ p += sprintf(p, "IO pad select : %s mA\n",
+ ((sc1c & 0x03) == 0x03) ? "10" :
+ ((sc1c & 0x02) == 0x02) ? "8" :
+ ((sc1c & 0x01) == 0x01) ? "6" :
+ ((sc1c & 0x00) == 0x00) ? "4" : "??");
+ hi = sc1e >> 4;
+ lo = sc1e & 0xf;
+ p += sprintf(p, "Status Polling Period : %d\n", hi);
+ p += sprintf(p, "Interrupt Check Status Polling Delay : %d\n", lo);
+#endif
+
static u8 pdc202xx_ratemask (ide_drive_t *drive)
{
u8 mode;
if (!(speed)) {
/* restore original pci-config space */
pci_write_config_dword(dev, drive_pci, drive_conf);
+ hwif->tuneproc(drive, 5);
return 0;
}
if (drive->addressing == 1) {
struct request *rq = HWGROUP(drive)->rq;
ide_hwif_t *hwif = HWIF(drive);
+// struct pci_dev *dev = hwif->pci_dev;
+// unsgned long high_16 = pci_resource_start(dev, 4);
unsigned long high_16 = hwif->dma_master;
unsigned long atapi_reg = high_16 + (hwif->channel ? 0x24 : 0x20);
u32 word_count = 0;
{
if (drive->addressing == 1) {
ide_hwif_t *hwif = HWIF(drive);
+// unsigned long high_16 = pci_resource_start(hwif->pci_dev, 4);
unsigned long high_16 = hwif->dma_master;
unsigned long atapi_reg = high_16 + (hwif->channel ? 0x24 : 0x20);
u8 clock = 0;
static int pdc202xx_old_ide_dma_test_irq(ide_drive_t *drive)
{
ide_hwif_t *hwif = HWIF(drive);
+// struct pci_dev *dev = hwif->pci_dev;
+// unsigned long high_16 = pci_resource_start(dev, 4);
unsigned long high_16 = hwif->dma_master;
u8 dma_stat = hwif->INB(hwif->dma_status);
u8 sc1d = hwif->INB((high_16 + 0x001d));
static void pdc202xx_reset_host (ide_hwif_t *hwif)
{
+#ifdef CONFIG_BLK_DEV_IDEDMA
+// unsigned long high_16 = hwif->dma_base - (8*(hwif->channel));
unsigned long high_16 = hwif->dma_master;
+#else /* !CONFIG_BLK_DEV_IDEDMA */
+ unsigned long high_16 = pci_resource_start(hwif->pci_dev, 4);
+#endif /* CONFIG_BLK_DEV_IDEDMA */
u8 udma_speed_flag = hwif->INB(high_16|0x001f);
hwif->OUTB((udma_speed_flag | 0x10), (high_16|0x001f));
pdc202xx_reset_host(hwif);
pdc202xx_reset_host(mate);
+#if 0
+ /*
+ * FIXME: Have to kick all the drives again :-/
+ * What a pain in the ACE!
+ */
+ if (hwif->present) {
+ u16 hunit = 0;
+ for (hunit = 0; hunit < MAX_DRIVES; ++hunit) {
+ ide_drive_t *hdrive = &hwif->drives[hunit];
+ if (hdrive->present) {
+ if (hwif->ide_dma_check)
+ hwif->ide_dma_check(hdrive);
+ else
+ hwif->tuneproc(hdrive, 5);
+ }
+ }
+ }
+ if (mate->present) {
+ u16 munit = 0;
+ for (munit = 0; munit < MAX_DRIVES; ++munit) {
+ ide_drive_t *mdrive = &mate->drives[munit];
+ if (mdrive->present) {
+ if (mate->ide_dma_check)
+ mate->ide_dma_check(mdrive);
+ else
+ mate->tuneproc(mdrive, 5);
+ }
+ }
+ }
+#else
hwif->tuneproc(drive, 5);
+#endif
+}
+
+/*
+ * Since SUN Cobalt is attempting to do this operation, I should disclose
+ * this has been a long time ago Thu Jul 27 16:40:57 2000 was the patch date
+ * HOTSWAP ATA Infrastructure.
+ */
+static int pdc202xx_tristate (ide_drive_t * drive, int state)
+{
+ ide_hwif_t *hwif = HWIF(drive);
+// unsigned long high_16 = hwif->dma_base - (8*(hwif->channel));
+ unsigned long high_16 = hwif->dma_master;
+ u8 sc1f = hwif->INB(high_16|0x001f);
+
+ if (!hwif)
+ return -EINVAL;
+
+// hwif->bus_state = state;
+
+ if (state) {
+ hwif->OUTB(sc1f | 0x08, (high_16|0x001f));
+ } else {
+ hwif->OUTB(sc1f & ~0x08, (high_16|0x001f));
+ }
+ return 0;
}
-static unsigned int __devinit init_chipset_pdc202xx(struct pci_dev *dev,
- const char *name)
+static unsigned int __devinit init_chipset_pdc202xx(struct pci_dev *dev, const char *name)
{
- /* This doesn't appear needed */
if (dev->resource[PCI_ROM_RESOURCE].start) {
pci_write_config_dword(dev, PCI_ROM_ADDRESS,
dev->resource[PCI_ROM_RESOURCE].start | PCI_ROM_ADDRESS_ENABLE);
- printk(KERN_INFO "%s: ROM enabled at 0x%08lx\n", name,
- (unsigned long)dev->resource[PCI_ROM_RESOURCE].start);
+ printk(KERN_INFO "%s: ROM enabled at 0x%08lx\n",
+ name, dev->resource[PCI_ROM_RESOURCE].start);
}
+ /*
+ * software reset - this is required because the bios
+ * will set UDMA timing on if the hdd supports it. The
+ * user may want to turn udma off. A bug in the pdc20262
+ * is that it cannot handle a downgrade in timing from
+ * UDMA to DMA. Disk accesses after issuing a set
+ * feature command will result in errors. A software
+ * reset leaves the timing registers intact,
+ * but resets the drives.
+ */
+#if 0
+ if ((dev->device == PCI_DEVICE_ID_PROMISE_20267) ||
+ (dev->device == PCI_DEVICE_ID_PROMISE_20265) ||
+ (dev->device == PCI_DEVICE_ID_PROMISE_20263) ||
+ (dev->device == PCI_DEVICE_ID_PROMISE_20262)) {
+ unsigned long high_16 = pci_resource_start(dev, 4);
+ byte udma_speed_flag = inb(high_16 + 0x001f);
+ outb(udma_speed_flag | 0x10, high_16 + 0x001f);
+ mdelay(100);
+ outb(udma_speed_flag & ~0x10, high_16 + 0x001f);
+ mdelay(2000); /* 2 seconds ?! */
+ }
+
+#endif
return dev->irq;
}
hwif->tuneproc = &config_chipset_for_pio;
hwif->quirkproc = &pdc202xx_quirkproc;
- if (hwif->pci_dev->device != PCI_DEVICE_ID_PROMISE_20246)
+ if (hwif->pci_dev->device != PCI_DEVICE_ID_PROMISE_20246) {
+ hwif->busproc = &pdc202xx_tristate;
hwif->resetproc = &pdc202xx_reset;
+ }
hwif->speedproc = &pdc202xx_tune_chipset;
hwif->mwdma_mask = 0x07;
hwif->swdma_mask = 0x07;
- hwif->err_stops_fifo = 1;
-
hwif->ide_dma_check = &pdc202xx_config_drive_xfer_rate;
hwif->ide_dma_lostirq = &pdc202xx_ide_dma_lostirq;
hwif->ide_dma_timeout = &pdc202xx_ide_dma_timeout;
"mirror fixed.\n", d->name);
}
}
+
+#if 0
+ if (dev->device == PCI_DEVICE_ID_PROMISE_20262)
+ if (e->reg && (pci_read_config_byte(dev, e->reg, &tmp) ||
+ (tmp & e->mask) != e->val))
+
+ if (d->enablebits[0].reg != d->enablebits[1].reg) {
+ d->enablebits[0].reg = d->enablebits[1].reg;
+ d->enablebits[0].mask = d->enablebits[1].mask;
+ d->enablebits[0].val = d->enablebits[1].val;
+ }
+#endif
+
return ide_setup_pci_device(dev, d);
}
"attached to I2O RAID controller.\n");
return -ENODEV;
}
+
+#if 0
+ {
+ u8 pri = 0, sec = 0;
+
+ if (e->reg && (pci_read_config_byte(dev, e->reg, &tmp) ||
+ (tmp & e->mask) != e->val))
+
+ if (d->enablebits[0].reg != d->enablebits[1].reg) {
+ d->enablebits[0].reg = d->enablebits[1].reg;
+ d->enablebits[0].mask = d->enablebits[1].mask;
+ d->enablebits[0].val = d->enablebits[1].val;
+ }
+ }
+#endif
+
return ide_setup_pci_device(dev, d);
}
.autodma = AUTODMA,
.bootable = OFF_BOARD,
.extra = 48,
+ .flags = IDEPCI_FLAG_FORCE_PDC,
},{ /* 2 */
.name = "PDC20263",
.init_setup = init_setup_pdc202ata4,
.autodma = AUTODMA,
.bootable = OFF_BOARD,
.extra = 48,
+ .flags = IDEPCI_FLAG_FORCE_PDC,
},{ /* 4 */
.name = "PDC20267",
.init_setup = init_setup_pdc202xx,
git://git.onelab.eu / linux-2.6.git / blobdiff