#define USE_IO_OPS
#endif
-#ifdef USE_IO_OPS
-#undef readb
-#undef readw
-#undef readl
-#undef writeb
-#undef writew
-#undef writel
-#define readb inb
-#define readw inw
-#define readl inl
-#define writeb outb
-#define writew outw
-#define writel outl
-#endif
-
/* Kernel compatibility defines, some common to David Hinds' PCMCIA package. */
/* This is only in the support-all-kernels source code. */
int mii_cnt; /* MII device addresses. */
unsigned char phys[2]; /* MII device addresses. */
struct mii_if_info mii;
+ void __iomem *mem;
};
static void reset_rx_descriptors(struct net_device *dev);
static void reset_tx_descriptors(struct net_device *dev);
-static void stop_nic_rx(long ioaddr, long crvalue)
+static void stop_nic_rx(void __iomem *ioaddr, long crvalue)
{
int delay = 0x1000;
- writel(crvalue & ~(CR_W_RXEN), ioaddr + TCRRCR);
+ iowrite32(crvalue & ~(CR_W_RXEN), ioaddr + TCRRCR);
while (--delay) {
- if ( (readl(ioaddr + TCRRCR) & CR_R_RXSTOP) == CR_R_RXSTOP)
+ if ( (ioread32(ioaddr + TCRRCR) & CR_R_RXSTOP) == CR_R_RXSTOP)
break;
}
}
-static void stop_nic_rxtx(long ioaddr, long crvalue)
+static void stop_nic_rxtx(void __iomem *ioaddr, long crvalue)
{
int delay = 0x1000;
- writel(crvalue & ~(CR_W_RXEN+CR_W_TXEN), ioaddr + TCRRCR);
+ iowrite32(crvalue & ~(CR_W_RXEN+CR_W_TXEN), ioaddr + TCRRCR);
while (--delay) {
- if ( (readl(ioaddr + TCRRCR) & (CR_R_RXSTOP+CR_R_TXSTOP))
+ if ( (ioread32(ioaddr + TCRRCR) & (CR_R_RXSTOP+CR_R_TXSTOP))
== (CR_R_RXSTOP+CR_R_TXSTOP) )
break;
}
int i, option, err, irq;
static int card_idx = -1;
char boardname[12];
- long ioaddr;
+ void __iomem *ioaddr;
+ unsigned long len;
unsigned int chip_id = ent->driver_data;
struct net_device *dev;
void *ring_space;
dma_addr_t ring_dma;
+#ifdef USE_IO_OPS
+ int bar = 0;
+#else
+ int bar = 1;
+#endif
/* when built into the kernel, we only print version if device is found */
#ifndef MODULE
if (i) return i;
pci_set_master(pdev);
-#ifdef USE_IO_OPS
- ioaddr = pci_resource_len(pdev, 0);
-#else
- ioaddr = pci_resource_len(pdev, 1);
-#endif
- if (ioaddr < MIN_REGION_SIZE) {
+ len = pci_resource_len(pdev, bar);
+ if (len < MIN_REGION_SIZE) {
printk(KERN_ERR "%s: region size %ld too small, aborting\n",
- boardname, ioaddr);
+ boardname, len);
return -ENODEV;
}
irq = pdev->irq;
-#ifdef USE_IO_OPS
- ioaddr = pci_resource_start(pdev, 0);
-#else
- ioaddr = (long) ioremap(pci_resource_start(pdev, 1),
- pci_resource_len(pdev, 1));
+ ioaddr = pci_iomap(pdev, bar, len);
if (!ioaddr) {
err = -ENOMEM;
goto err_out_res;
}
-#endif
-
+
dev = alloc_etherdev(sizeof(struct netdev_private));
if (!dev) {
err = -ENOMEM;
/* read ethernet id */
for (i = 0; i < 6; ++i)
- dev->dev_addr[i] = readb(ioaddr + PAR0 + i);
+ dev->dev_addr[i] = ioread8(ioaddr + PAR0 + i);
/* Reset the chip to erase previous misconfiguration. */
- writel(0x00000001, ioaddr + BCR);
+ iowrite32(0x00000001, ioaddr + BCR);
- dev->base_addr = ioaddr;
+ dev->base_addr = (unsigned long)ioaddr;
dev->irq = irq;
/* Make certain the descriptor lists are aligned. */
- np = dev->priv;
+ np = netdev_priv(dev);
+ np->mem = ioaddr;
spin_lock_init(&np->lock);
np->pci_dev = pdev;
np->flags = skel_netdrv_tbl[chip_id].flags;
np->phys[0] = 32;
/* 89/6/23 add, (begin) */
/* get phy type */
- if (readl(ioaddr + PHYIDENTIFIER) == MysonPHYID)
+ if (ioread32(ioaddr + PHYIDENTIFIER) == MysonPHYID)
np->PHYType = MysonPHY;
else
np->PHYType = OtherPHY;
if (np->flags == HAS_MII_XCVR)
mdio_write(dev, np->phys[0], MII_ADVERTISE, ADVERTISE_FULL);
else
- writel(ADVERTISE_FULL, ioaddr + ANARANLPAR);
+ iowrite32(ADVERTISE_FULL, ioaddr + ANARANLPAR);
np->mii.force_media = 1;
}
if (err)
goto err_out_free_tx;
- printk(KERN_INFO "%s: %s at 0x%lx, ",
+ printk(KERN_INFO "%s: %s at %p, ",
dev->name, skel_netdrv_tbl[chip_id].chip_name, ioaddr);
for (i = 0; i < 5; i++)
printk("%2.2x:", dev->dev_addr[i]);
err_out_free_dev:
free_netdev(dev);
err_out_unmap:
-#ifndef USE_IO_OPS
- iounmap((void *)ioaddr);
+ pci_iounmap(pdev, ioaddr);
err_out_res:
-#endif
pci_release_regions(pdev);
return err;
}
struct net_device *dev = pci_get_drvdata(pdev);
if (dev) {
- struct netdev_private *np = dev->priv;
+ struct netdev_private *np = netdev_priv(dev);
pci_free_consistent(pdev, TX_TOTAL_SIZE, np->tx_ring,
np->tx_ring_dma);
pci_free_consistent(pdev, RX_TOTAL_SIZE, np->rx_ring,
np->rx_ring_dma);
unregister_netdev(dev);
-#ifndef USE_IO_OPS
- iounmap((void *)dev->base_addr);
-#endif
+ pci_iounmap(pdev, np->mem);
free_netdev(dev);
pci_release_regions(pdev);
pci_set_drvdata(pdev, NULL);
}
-static ulong m80x_send_cmd_to_phy(long miiport, int opcode, int phyad, int regad)
+static ulong m80x_send_cmd_to_phy(void __iomem *miiport, int opcode, int phyad, int regad)
{
ulong miir;
int i;
unsigned int mask, data;
/* enable MII output */
- miir = (ulong) readl(miiport);
+ miir = (ulong) ioread32(miiport);
miir &= 0xfffffff0;
miir |= MASK_MIIR_MII_WRITE + MASK_MIIR_MII_MDO;
for (i = 0; i < 32; i++) {
/* low MDC; MDO is already high (miir) */
miir &= ~MASK_MIIR_MII_MDC;
- writel(miir, miiport);
+ iowrite32(miir, miiport);
/* high MDC */
miir |= MASK_MIIR_MII_MDC;
- writel(miir, miiport);
+ iowrite32(miir, miiport);
}
/* calculate ST+OP+PHYAD+REGAD+TA */
if (mask & data)
miir |= MASK_MIIR_MII_MDO;
- writel(miir, miiport);
+ iowrite32(miir, miiport);
/* high MDC */
miir |= MASK_MIIR_MII_MDC;
- writel(miir, miiport);
+ iowrite32(miir, miiport);
udelay(30);
/* next */
static int mdio_read(struct net_device *dev, int phyad, int regad)
{
- long miiport = dev->base_addr + MANAGEMENT;
+ struct netdev_private *np = netdev_priv(dev);
+ void __iomem *miiport = np->mem + MANAGEMENT;
ulong miir;
unsigned int mask, data;
while (mask) {
/* low MDC */
miir &= ~MASK_MIIR_MII_MDC;
- writel(miir, miiport);
+ iowrite32(miir, miiport);
/* read MDI */
- miir = readl(miiport);
+ miir = ioread32(miiport);
if (miir & MASK_MIIR_MII_MDI)
data |= mask;
/* high MDC, and wait */
miir |= MASK_MIIR_MII_MDC;
- writel(miir, miiport);
+ iowrite32(miir, miiport);
udelay(30);
/* next */
/* low MDC */
miir &= ~MASK_MIIR_MII_MDC;
- writel(miir, miiport);
+ iowrite32(miir, miiport);
return data & 0xffff;
}
static void mdio_write(struct net_device *dev, int phyad, int regad, int data)
{
- long miiport = dev->base_addr + MANAGEMENT;
+ struct netdev_private *np = netdev_priv(dev);
+ void __iomem *miiport = np->mem + MANAGEMENT;
ulong miir;
unsigned int mask;
miir &= ~(MASK_MIIR_MII_MDC + MASK_MIIR_MII_MDO);
if (mask & data)
miir |= MASK_MIIR_MII_MDO;
- writel(miir, miiport);
+ iowrite32(miir, miiport);
/* high MDC */
miir |= MASK_MIIR_MII_MDC;
- writel(miir, miiport);
+ iowrite32(miir, miiport);
/* next */
mask >>= 1;
/* low MDC */
miir &= ~MASK_MIIR_MII_MDC;
- writel(miir, miiport);
+ iowrite32(miir, miiport);
}
static int netdev_open(struct net_device *dev)
{
- struct netdev_private *np = dev->priv;
- long ioaddr = dev->base_addr;
+ struct netdev_private *np = netdev_priv(dev);
+ void __iomem *ioaddr = np->mem;
int i;
- writel(0x00000001, ioaddr + BCR); /* Reset */
+ iowrite32(0x00000001, ioaddr + BCR); /* Reset */
if (request_irq(dev->irq, &intr_handler, SA_SHIRQ, dev->name, dev))
return -EAGAIN;
for (i = 0; i < 3; i++)
- writew(((unsigned short*)dev->dev_addr)[i],
+ iowrite16(((unsigned short*)dev->dev_addr)[i],
ioaddr + PAR0 + i*2);
init_ring(dev);
- writel(np->rx_ring_dma, ioaddr + RXLBA);
- writel(np->tx_ring_dma, ioaddr + TXLBA);
+ iowrite32(np->rx_ring_dma, ioaddr + RXLBA);
+ iowrite32(np->tx_ring_dma, ioaddr + TXLBA);
/* Initialize other registers. */
/* Configure the PCI bus bursts and FIFO thresholds.
np->crvalue |= CR_W_ENH; /* set enhanced bit */
np->imrvalue |= ETI;
}
- writel(np->bcrvalue, ioaddr + BCR);
+ iowrite32(np->bcrvalue, ioaddr + BCR);
if (dev->if_port == 0)
dev->if_port = np->default_port;
- writel(0, ioaddr + RXPDR);
+ iowrite32(0, ioaddr + RXPDR);
// 89/9/1 modify,
// np->crvalue = 0x00e40001; /* tx store and forward, tx/rx enable */
np->crvalue |= 0x00e40001; /* tx store and forward, tx/rx enable */
netif_start_queue(dev);
/* Clear and Enable interrupts by setting the interrupt mask. */
- writel(FBE | TUNF | CNTOVF | RBU | TI | RI, ioaddr + ISR);
- writel(np->imrvalue, ioaddr + IMR);
+ iowrite32(FBE | TUNF | CNTOVF | RBU | TI | RI, ioaddr + ISR);
+ iowrite32(np->imrvalue, ioaddr + IMR);
if (debug)
printk(KERN_DEBUG "%s: Done netdev_open().\n", dev->name);
/* input : dev... pointer to the adapter block. */
/* output : none. */
{
- struct netdev_private *np = dev->priv;
+ struct netdev_private *np = netdev_priv(dev);
unsigned int i, DelayTime = 0x1000;
np->linkok = 0;
if (np->PHYType == MysonPHY) {
for (i = 0; i < DelayTime; ++i) {
- if (readl(dev->base_addr + BMCRSR) & LinkIsUp2) {
+ if (ioread32(np->mem + BMCRSR) & LinkIsUp2) {
np->linkok = 1;
return;
}
static void getlinktype(struct net_device *dev)
{
- struct netdev_private *np = dev->priv;
+ struct netdev_private *np = netdev_priv(dev);
if (np->PHYType == MysonPHY) { /* 3-in-1 case */
- if (readl(dev->base_addr + TCRRCR) & CR_R_FD)
+ if (ioread32(np->mem + TCRRCR) & CR_R_FD)
np->duplexmode = 2; /* full duplex */
else
np->duplexmode = 1; /* half duplex */
- if (readl(dev->base_addr + TCRRCR) & CR_R_PS10)
+ if (ioread32(np->mem + TCRRCR) & CR_R_PS10)
np->line_speed = 1; /* 10M */
else
np->line_speed = 2; /* 100M */
/* Take lock before calling this */
static void allocate_rx_buffers(struct net_device *dev)
{
- struct netdev_private *np = dev->priv;
+ struct netdev_private *np = netdev_priv(dev);
/* allocate skb for rx buffers */
while (np->really_rx_count != RX_RING_SIZE) {
static void netdev_timer(unsigned long data)
{
struct net_device *dev = (struct net_device *) data;
- struct netdev_private *np = dev->priv;
- long ioaddr = dev->base_addr;
+ struct netdev_private *np = netdev_priv(dev);
+ void __iomem *ioaddr = np->mem;
int old_crvalue = np->crvalue;
unsigned int old_linkok = np->linkok;
unsigned long flags;
if (debug)
printk(KERN_DEBUG "%s: Media selection timer tick, status %8.8x "
- "config %8.8x.\n", dev->name, readl(ioaddr + ISR),
- readl(ioaddr + TCRRCR));
+ "config %8.8x.\n", dev->name, ioread32(ioaddr + ISR),
+ ioread32(ioaddr + TCRRCR));
spin_lock_irqsave(&np->lock, flags);
getlinktype(dev);
if (np->crvalue != old_crvalue) {
stop_nic_rxtx(ioaddr, np->crvalue);
- writel(np->crvalue, ioaddr + TCRRCR);
+ iowrite32(np->crvalue, ioaddr + TCRRCR);
}
}
}
/* Reset chip and disable rx, tx and interrupts */
static void reset_and_disable_rxtx(struct net_device *dev)
{
- long ioaddr = dev->base_addr;
+ struct netdev_private *np = netdev_priv(dev);
+ void __iomem *ioaddr = np->mem;
int delay=51;
/* Reset the chip's Tx and Rx processes. */
stop_nic_rxtx(ioaddr, 0);
/* Disable interrupts by clearing the interrupt mask. */
- writel(0, ioaddr + IMR);
+ iowrite32(0, ioaddr + IMR);
/* Reset the chip to erase previous misconfiguration. */
- writel(0x00000001, ioaddr + BCR);
+ iowrite32(0x00000001, ioaddr + BCR);
/* Ueimor: wait for 50 PCI cycles (and flush posted writes btw).
We surely wait too long (address+data phase). Who cares? */
while (--delay) {
- readl(ioaddr + BCR);
+ ioread32(ioaddr + BCR);
rmb();
}
}
/* Restore chip after reset */
static void enable_rxtx(struct net_device *dev)
{
- struct netdev_private *np = dev->priv;
- long ioaddr = dev->base_addr;
+ struct netdev_private *np = netdev_priv(dev);
+ void __iomem *ioaddr = np->mem;
reset_rx_descriptors(dev);
- writel(np->tx_ring_dma + ((char*)np->cur_tx - (char*)np->tx_ring),
+ iowrite32(np->tx_ring_dma + ((char*)np->cur_tx - (char*)np->tx_ring),
ioaddr + TXLBA);
- writel(np->rx_ring_dma + ((char*)np->cur_rx - (char*)np->rx_ring),
+ iowrite32(np->rx_ring_dma + ((char*)np->cur_rx - (char*)np->rx_ring),
ioaddr + RXLBA);
- writel(np->bcrvalue, ioaddr + BCR);
+ iowrite32(np->bcrvalue, ioaddr + BCR);
- writel(0, ioaddr + RXPDR);
+ iowrite32(0, ioaddr + RXPDR);
__set_rx_mode(dev); /* changes np->crvalue, writes it into TCRRCR */
/* Clear and Enable interrupts by setting the interrupt mask. */
- writel(FBE | TUNF | CNTOVF | RBU | TI | RI, ioaddr + ISR);
- writel(np->imrvalue, ioaddr + IMR);
+ iowrite32(FBE | TUNF | CNTOVF | RBU | TI | RI, ioaddr + ISR);
+ iowrite32(np->imrvalue, ioaddr + IMR);
- writel(0, ioaddr + TXPDR);
+ iowrite32(0, ioaddr + TXPDR);
}
static void reset_timer(unsigned long data)
{
struct net_device *dev = (struct net_device *) data;
- struct netdev_private *np = dev->priv;
+ struct netdev_private *np = netdev_priv(dev);
unsigned long flags;
printk(KERN_WARNING "%s: resetting tx and rx machinery\n", dev->name);
static void tx_timeout(struct net_device *dev)
{
- struct netdev_private *np = dev->priv;
- long ioaddr = dev->base_addr;
+ struct netdev_private *np = netdev_priv(dev);
+ void __iomem *ioaddr = np->mem;
unsigned long flags;
int i;
printk(KERN_WARNING "%s: Transmit timed out, status %8.8x,"
- " resetting...\n", dev->name, readl(ioaddr + ISR));
+ " resetting...\n", dev->name, ioread32(ioaddr + ISR));
{
printk(KERN_DEBUG " Rx ring %p: ", np->rx_ring);
/* Initialize the Rx and Tx rings, along with various 'dev' bits. */
static void init_ring(struct net_device *dev)
{
- struct netdev_private *np = dev->priv;
+ struct netdev_private *np = netdev_priv(dev);
int i;
/* initialize rx variables */
static int start_tx(struct sk_buff *skb, struct net_device *dev)
{
- struct netdev_private *np = dev->priv;
+ struct netdev_private *np = netdev_priv(dev);
unsigned long flags;
spin_lock_irqsave(&np->lock, flags);
if (np->free_tx_count < 2)
netif_stop_queue(dev);
++np->really_tx_count;
- writel(0, dev->base_addr + TXPDR);
+ iowrite32(0, np->mem + TXPDR);
dev->trans_start = jiffies;
spin_unlock_irqrestore(&np->lock, flags);
/* Chip probably hosed tx ring. Clean up. */
static void reset_tx_descriptors(struct net_device *dev)
{
- struct netdev_private *np = dev->priv;
+ struct netdev_private *np = netdev_priv(dev);
struct fealnx_desc *cur;
int i;
/* Take lock and stop rx before calling this */
static void reset_rx_descriptors(struct net_device *dev)
{
- struct netdev_private *np = dev->priv;
+ struct netdev_private *np = netdev_priv(dev);
struct fealnx_desc *cur = np->cur_rx;
int i;
cur = cur->next_desc_logical;
}
- writel(np->rx_ring_dma + ((char*)np->cur_rx - (char*)np->rx_ring),
- dev->base_addr + RXLBA);
+ iowrite32(np->rx_ring_dma + ((char*)np->cur_rx - (char*)np->rx_ring),
+ np->mem + RXLBA);
}
static irqreturn_t intr_handler(int irq, void *dev_instance, struct pt_regs *rgs)
{
struct net_device *dev = (struct net_device *) dev_instance;
- struct netdev_private *np = dev->priv;
- long ioaddr = dev->base_addr;
+ struct netdev_private *np = netdev_priv(dev);
+ void __iomem *ioaddr = np->mem;
long boguscnt = max_interrupt_work;
unsigned int num_tx = 0;
int handled = 0;
spin_lock(&np->lock);
- writel(0, ioaddr + IMR);
+ iowrite32(0, ioaddr + IMR);
do {
- u32 intr_status = readl(ioaddr + ISR);
+ u32 intr_status = ioread32(ioaddr + ISR);
/* Acknowledge all of the current interrupt sources ASAP. */
- writel(intr_status, ioaddr + ISR);
+ iowrite32(intr_status, ioaddr + ISR);
if (debug)
printk(KERN_DEBUG "%s: Interrupt, status %4.4x.\n", dev->name,
// };
if (intr_status & TUNF)
- writel(0, ioaddr + TXPDR);
+ iowrite32(0, ioaddr + TXPDR);
if (intr_status & CNTOVF) {
/* missed pkts */
- np->stats.rx_missed_errors += readl(ioaddr + TALLY) & 0x7fff;
+ np->stats.rx_missed_errors += ioread32(ioaddr + TALLY) & 0x7fff;
/* crc error */
np->stats.rx_crc_errors +=
- (readl(ioaddr + TALLY) & 0x7fff0000) >> 16;
+ (ioread32(ioaddr + TALLY) & 0x7fff0000) >> 16;
}
if (intr_status & (RI | RBU)) {
else {
stop_nic_rx(ioaddr, np->crvalue);
reset_rx_descriptors(dev);
- writel(np->crvalue, ioaddr + TCRRCR);
+ iowrite32(np->crvalue, ioaddr + TCRRCR);
}
}
if (np->crvalue & CR_W_ENH) {
long data;
- data = readl(ioaddr + TSR);
+ data = ioread32(ioaddr + TSR);
np->stats.tx_errors += (data & 0xff000000) >> 24;
np->stats.tx_aborted_errors += (data & 0xff000000) >> 24;
np->stats.tx_window_errors += (data & 0x00ff0000) >> 16;
/* read the tally counters */
/* missed pkts */
- np->stats.rx_missed_errors += readl(ioaddr + TALLY) & 0x7fff;
+ np->stats.rx_missed_errors += ioread32(ioaddr + TALLY) & 0x7fff;
/* crc error */
- np->stats.rx_crc_errors += (readl(ioaddr + TALLY) & 0x7fff0000) >> 16;
+ np->stats.rx_crc_errors += (ioread32(ioaddr + TALLY) & 0x7fff0000) >> 16;
if (debug)
printk(KERN_DEBUG "%s: exiting interrupt, status=%#4.4x.\n",
- dev->name, readl(ioaddr + ISR));
+ dev->name, ioread32(ioaddr + ISR));
- writel(np->imrvalue, ioaddr + IMR);
+ iowrite32(np->imrvalue, ioaddr + IMR);
spin_unlock(&np->lock);
for clarity and better register allocation. */
static int netdev_rx(struct net_device *dev)
{
- struct netdev_private *np = dev->priv;
- long ioaddr = dev->base_addr;
+ struct netdev_private *np = netdev_priv(dev);
+ void __iomem *ioaddr = np->mem;
/* If EOP is set on the next entry, it's a new packet. Send it up. */
while (!(np->cur_rx->status & RXOWN) && np->cur_rx->skbuff) {
} else { /* rx error, need to reset this chip */
stop_nic_rx(ioaddr, np->crvalue);
reset_rx_descriptors(dev);
- writel(np->crvalue, ioaddr + TCRRCR);
+ iowrite32(np->crvalue, ioaddr + TCRRCR);
}
break; /* exit the while loop */
}
static struct net_device_stats *get_stats(struct net_device *dev)
{
- long ioaddr = dev->base_addr;
- struct netdev_private *np = dev->priv;
+ struct netdev_private *np = netdev_priv(dev);
+ void __iomem *ioaddr = np->mem;
/* The chip only need report frame silently dropped. */
if (netif_running(dev)) {
- np->stats.rx_missed_errors += readl(ioaddr + TALLY) & 0x7fff;
- np->stats.rx_crc_errors += (readl(ioaddr + TALLY) & 0x7fff0000) >> 16;
+ np->stats.rx_missed_errors += ioread32(ioaddr + TALLY) & 0x7fff;
+ np->stats.rx_crc_errors += (ioread32(ioaddr + TALLY) & 0x7fff0000) >> 16;
}
return &np->stats;
/* for dev->set_multicast_list */
static void set_rx_mode(struct net_device *dev)
{
- spinlock_t *lp = &((struct netdev_private *)dev->priv)->lock;
+ spinlock_t *lp = &((struct netdev_private *)netdev_priv(dev))->lock;
unsigned long flags;
spin_lock_irqsave(lp, flags);
__set_rx_mode(dev);
/* Take lock before calling */
static void __set_rx_mode(struct net_device *dev)
{
- struct netdev_private *np = dev->priv;
- long ioaddr = dev->base_addr;
+ struct netdev_private *np = netdev_priv(dev);
+ void __iomem *ioaddr = np->mem;
u32 mc_filter[2]; /* Multicast hash filter */
u32 rx_mode;
stop_nic_rxtx(ioaddr, np->crvalue);
- writel(mc_filter[0], ioaddr + MAR0);
- writel(mc_filter[1], ioaddr + MAR1);
+ iowrite32(mc_filter[0], ioaddr + MAR0);
+ iowrite32(mc_filter[1], ioaddr + MAR1);
np->crvalue &= ~CR_W_RXMODEMASK;
np->crvalue |= rx_mode;
- writel(np->crvalue, ioaddr + TCRRCR);
+ iowrite32(np->crvalue, ioaddr + TCRRCR);
}
static void netdev_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
{
- struct netdev_private *np = dev->priv;
+ struct netdev_private *np = netdev_priv(dev);
strcpy(info->driver, DRV_NAME);
strcpy(info->version, DRV_VERSION);
static int netdev_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
{
- struct netdev_private *np = dev->priv;
+ struct netdev_private *np = netdev_priv(dev);
int rc;
spin_lock_irq(&np->lock);
static int netdev_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
{
- struct netdev_private *np = dev->priv;
+ struct netdev_private *np = netdev_priv(dev);
int rc;
spin_lock_irq(&np->lock);
static int netdev_nway_reset(struct net_device *dev)
{
- struct netdev_private *np = dev->priv;
+ struct netdev_private *np = netdev_priv(dev);
return mii_nway_restart(&np->mii);
}
static u32 netdev_get_link(struct net_device *dev)
{
- struct netdev_private *np = dev->priv;
+ struct netdev_private *np = netdev_priv(dev);
return mii_link_ok(&np->mii);
}
static int mii_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
{
- struct netdev_private *np = dev->priv;
+ struct netdev_private *np = netdev_priv(dev);
int rc;
if (!netif_running(dev))
static int netdev_close(struct net_device *dev)
{
- long ioaddr = dev->base_addr;
- struct netdev_private *np = dev->priv;
+ struct netdev_private *np = netdev_priv(dev);
+ void __iomem *ioaddr = np->mem;
int i;
netif_stop_queue(dev);
/* Disable interrupts by clearing the interrupt mask. */
- writel(0x0000, ioaddr + IMR);
+ iowrite32(0x0000, ioaddr + IMR);
/* Stop the chip's Tx and Rx processes. */
stop_nic_rxtx(ioaddr, 0);
git://git.onelab.eu / linux-2.6.git / blobdiff