GM_TXCR_FORCE_JAM = 1<<15, /* Bit 15: Force Jam / Flow-Control */
GM_TXCR_CRC_DIS = 1<<14, /* Bit 14: Disable insertion of CRC */
GM_TXCR_PAD_DIS = 1<<13, /* Bit 13: Disable padding of packets */
- GM_TXCR_COL_THR_MSK = 7<<10, /* Bit 12..10: Collision Threshold */
+ GM_TXCR_COL_THR_MSK = 1<<10, /* Bit 12..10: Collision Threshold */
};
#define TX_COL_THR(x) (((x)<<10) & GM_TXCR_COL_THR_MSK)
-#define TX_COL_DEF 0x04 /* late collision after 64 byte */
+#define TX_COL_DEF 0x04
/* GM_RX_CTRL 16 bit r/w Receive Control Register */
enum {
struct skge_hw {
void __iomem *regs;
struct pci_dev *pdev;
- spinlock_t hw_lock;
u32 intr_mask;
struct net_device *dev[2];
u32 ram_size;
u32 ram_offset;
u16 phy_addr;
- struct work_struct phy_work;
- struct mutex phy_mutex;
+
+ struct tasklet_struct ext_tasklet;
+ spinlock_t phy_lock;
+ spinlock_t hw_lock;
};
enum {
int port;
spinlock_t tx_lock;
+ u32 tx_avail;
struct skge_ring tx_ring;
struct skge_ring rx_ring;